Datasheet

Classic PCI Configuration Space
48
March 5 2007 − June 2011SCPS154C
4.21 Prefetchable Memory Limit Register
This read/write register specifies the upper limit of the prefetchable memory addresses that the bridge
forwards downstream. See Table 4−12 for a complete description of the register contents.
PCI register offset: 26h
Register type: Read-only, Read/Write
Default value: 0001h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Table 4−12. Prefetchable Memory Limit Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:4 PRELIMIT RW
Prefetchable memory limit. Defines the highest address of the prefetchable memory address range
that determines when to forward memory transactions from one interface to the other. These bits
correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be
FFFFFh. The prefetchable limit upper 32 bits register (offset 2Ch, see Section 4.23) specifies the
bit [63:32] of the 64-bit prefetchable memory address.
3:0 64BIT R
64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this
memory window.
4.22 Prefetchable Base Upper 32 Bits Register
This read/write register specifies the upper 32 bits of the prefetchable memory base register. See Table 4−13
for a complete description of the register contents.
PCI register offset: 28h
Register type: Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−13. Prefetchable Base Upper 32 Bits Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:0 PREBASE RW
Prefetchable memory base upper 32 bits. Defines the upper 32 bits of the lowest address of the
prefetchable memory address range that determines when to forward memory transactions
downstream.
4.23 Prefetchable Limit Upper 32 Bits Register
This read/write register specifies the upper 32 bits of the prefetchable memory limit register. See Table 4−14
for a complete description of the register contents.
PCI register offset: 2Ch
Register type: Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−14. Prefetchable Limit Upper 32 Bits Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:0 PRELIMIT RW
Prefetchable memory limit upper 32 bits. Defines the upper 32 bits of the highest address of the
prefetchable memory address range that determines when to forward memory transactions
downstream.
Not Recommended for New Designs