Datasheet

Classic PCI Configuration Space

March 5 2007 − June 2011SCPS154C

4.5 Class Code and Revision ID Register

This read-only register categorizes the base class, subclass, and programming interface of the bridge. The

base class is 06h, identifying the device as a bridge. The subclass is 04h, identifying the function as a

PCI-to-PCI bridge, and the programming interface is 00h. Furthermore, the TI device revision is indicated in

the lower byte (03h). See Table 4−4 for a complete description of the register contents.

PCI register offset: 08h

Default value: 0604 0003

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Table 4−4. Class Code and Revision ID Register Description

BIT FIELD NAME ACCESS DESCRIPTION

31:24 BASECLASS R Base class. This field returns 06h when read, which classifies the function as a bridge device.

23:16 SUBCLASS R Subclass. This field returns 04h when read, which classifies the function as a PCI-to-PCI bridge.

15:8 PGMIF R Programming interface. This field returns 00h when read.

7:0 CHIPREV R Silicon revision. This field returns the silicon revision of the function.

4.6 Cache Line Size Register

This read/write cache line size register is used by the bridge to determine how much data to prefetch when

handling delayed read transactions. The value in this register must be programmed to a power of 2. Any written

odd value (bit 0 = 1b) or value greater than 32 DWORDs is treated as 0 DWORDs.

PCI register offset: 0Ch

Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.7 Primary Latency Timer Register

This read-only register has no meaningful context for a PCI Express device and returns 00h when read.

PCI register offset: 0Dh

Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.8 Header Type Register

This read-only register indicates that this function has a type one PCI header. Bit 7 of this register is 0b

indicating that the bridge is a single-function device.

PCI register offset: 0Eh

Default value: 01h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 1

Not Recommended for New Designs