Datasheet

Feature/Protocol Descriptions
33
March 5 2007 − June 2011 SCPS154C
Table 3−10. EEPROM Register Loading Map (Continued)
SERIAL EEPROM
WORD ADDRESS
BYTE DESCRIPTION
27h
PCI F4h, Link_Enh, byte 0, bits 7, 2, 1
OHCI 50h, host controller control, bit 23
[7]
Link_Enh
enab_unfair
[6]
HC Control Program
Phy Enable
[5:3]
RSVD
[2]
Link_Enh
bit 2
[1]
Link_Enh
enab_accel
[0]
RSVD
28h
Mini−ROM Address, this byte indicates the MINI ROM offset into the EEPROM
00h = No MINI ROM
01h to FFh = MINI ROM offset
29h OHCI 24h, GUIDHi, byte 0
2Ah OHCI 25h, GUIDHi, byte 1
2Bh OHCI 26h, GUIDHi, byte 2
2Ch OHCI 27h, GUIDHi, byte 3
2Dh OHCI 28h, GUIDLo, byte 0
2Eh OHCI 29h, GUIDLo, byte 1
2Fh OHCI 2Ah, GUIDLo, byte 2
30h OHCI 2Bh, GUIDLo, byte 3
31h Reserved—No bits loaded
32h PCI F5h, Link_Enh, byte 1, bits 7, 6, 5, 4
33h PCI F0h, PCI miscellaneous, byte 0, bits 7, 4, 2, 1, 0
34h PCI F1h, PCI miscellaneous, byte 1, bits 1, 0
35h Reserved—No bits loaded
36h Reserved—No bits loaded
37h Reserved—No bits loaded
38h PCI ECh, PCI PHY control, bits 7, 3, 1
39h End-of-list indicator (80h)
This format must be explicitly followed for the bridge to correctly load initialization values from a serial
EEPROM. All byte locations must be considered when programming the EEPROM.
The serial EEPROM is addressed by the bridge at slave address 1010 000b. This slave address is internally
hardwired and cannot be changed by the system designer. Therefore, all three hardware address bits for the
EEPROM are tied to V
SS
to achieve this address. The serial EEPROM in the sample application circuit
(Figure 3−7) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to the
chip, and the sample application shows these terminal inputs tied to V
SS
.
During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is
asserted. After the download is finished, bit 0 (ROM_ERR) in the serial-bus control and status register may
be monitored to verify a successful download.
3.6.4 Accessing Serial-Bus Devices Through Software
The bridge provides a programming mechanism to control serial-bus devices through system software. The
programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−11 lists
the registers that program a serial-bus device through software.
Not Recommended for New Designs