Datasheet

Feature/Protocol Descriptions
31
March 5 2007 − June 2011 SCPS154C
Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
Slave Address Word Address
R/W
Sb6 b4b5 b3 b2 b1 b0 1 A
Slave Address
S/P = Start/Stop ConditionM = Master Acknowledgement
b7 b6 b4b5 b3 b2 b1 b0 M P
Data Byte
Start
Restart R/W
A = Slave Acknowledgement
Stop
Figure 3−11. Serial-Bus Protocol—Byte Read
Figure 3−12 illustrates the serial interface protocol during a multi-byte serial EEPROM download. The
serial-bus protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes
are transferred. The number of transferred data bytes is controlled by the bridge master. After each data byte,
the bridge master issues acknowledge (logic low) if more data bytes are requested. The transfer ends after
a bridge master no acknowledge (logic high) followed by a stop condition.
S1 10 00000 00000000AA
Slave Address Word Address
R/W
Data Byte 1 Data Byte 2 Data Byte 3 M PMM
M = Master Acknowledgement
S/P = Start/Stop ConditionA = Slave Acknowledgement
Data Byte 0 M
S1 10 00001A
Restart
R/W
Slave Address
Start
Figure 3−12. Serial-Bus Protocol—Multibyte Read
Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of the
three previous serial-bus protocol figures illustrates the PROT_SEL bit default (logic low). When this control
bit is asserted, the word address and corresponding acknowledge are removed from the serial-bus protocol.
This feature allows the system designer a second serial-bus protocol option when selecting external EEPROM
devices.
3.6.3 Serial-Bus EEPROM Application
The registers and corresponding bits that are loaded through the EEPROM are provided in Table 3−10.
Not Recommended for New Designs