Datasheet

Feature/Protocol Descriptions
28
March 5 2007 − June 2011SCPS154C
3.5 PCI Interrupt Conversion to PCI Express Messages
The bridge converts interrupts from the PCI bus sideband interrupt signals to PCI Express interrupt messages.
Since the 1394a OHCI only generates INTA
interrupts, only PCI Express INTA messages are generated by
the bridge.
PCI Express Assert_INTA messages are generated when the 1394a OHCI signals an INTA
interrupt. The
requester ID portion of the Assert_INTA message uses the value stored in the primary bus number register
(see Section 4.11) as the bus number, 0 as the device number, and 0 as the function number. The tag field
for each Assert_INTA message is 00h.
PCI Express Deassert_INTA messages are generated when the 1394a OHCI deasserts the INTA
interrupt.
The requester ID portion of the Deassert_INTA message uses the value stored in the primary bus number
register as the bus number, 0 as the device number, and 0 as the function number. The Tag field for each
Deassert_INTA message is 00h.
Figure 3−5 and Figure 3−6 illustrate the format for both the assert and deassert INTA messages.
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0>
R
Fmt Type
R
TC
Reserved
T
E Attr
R
Length
Byte 0>
R
0 1 1 0 1 0 0
R
0 0 0
Reserved
D P 0 0
R
0 0 0 0 0 0 0 0 0 0
Byte 4>
Requester ID
Tag
Code
Byte 4>
Requester ID
Tag
0 0 1 0 0 0 0 0
Byte 8>
Reserved
Byte 12>
Reserved
Figure 3−5. PCI Express ASSERT_INTA Message
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0>
R
Fmt Type
R
TC
Reserved
T
E Attr
R
Length
Byte 0>
R
0 1 1 0 1 0 0
R
0 0 0
Reserved
D P 0 0
R
0 0 0 0 0 0 0 0 0 0
Byte 4>
Requester ID
Tag
Code
Byte 4>
Requester ID
Tag
0 0 1 0 0 1 0 0
Byte 8>
Reserved
Byte 12>
Reserved
Figure 3−6. PCI Express DEASSERT_INTX Message
3.6 Two-Wire Serial-Bus Interface
The bridge provides a two-wire serial-bus interface to load subsystem identification information and specific
register defaults from an external EEPROM. The serial-bus interface signals (SCL and SDA) are shared with
two of the GPIO terminals (4 and 5). If the serial bus interface is enabled, then the GPIO4 and GPIO5 terminals
are disabled. If the serial bus interface is disabled, then the GPIO terminals operate as described in
Section 3.9.
3.6.1 Serial-Bus Interface Implementation
To enable the serial-bus interface, a pullup resistor must be implemented on the SDA signal. At the rising edge
of PERST
or GRST, whichever occurs later in time, the SDA terminal is checked for a pullup resistor. If one
is detected, then bit 3 (SBDETECT) in the serial-bus control and status register (see Section 4.58) is set.
Software may disable the serial-bus interface at any time by writing a 0b to the SBDETECT bit. If no external
EEPROM is required, then the serial-bus interface is permanently disabled by attaching a pulldown resistor
to the SDA signal.
Not Recommended for New Designs