Datasheet

Feature/Protocol Descriptions
27
March 5 2007 − June 2011 SCPS154C
Table 3−9. 32-Phase, WRR Arbiter Registers
PCI OFFSET REGISTER NAME DESCRIPTION
Classic PCI configuration
register D4h
General control
(see Section 4.65)
Bit 25 (STRICT_PRIORITY_EN) equal to 0b enables either hardware-fixed,
round-robin or 32-phase, WRR arbitration mode.
PCI Express VC extended
configuration register 15Ch
Port VC control
(see Section 5.19)
Bit 0 (LOAD_VC_TABLE) when written with a 1b transfers the VC arbitration table
configuration register values to the internal registers used by the VC arbiter.
Bits 3:1 (VC_ARB_SELECT) equal to 001b enable the 32-phase, WRR arbitration
mode.
PCI Express VC extended
configuration register 15Eh
Port VC status
(see Section 5.20)
Bit 0 (VC_TABLE_STATUS) equal to 1b indicates that the VC arbitration table
configuration registers were updated but not loaded into the internal arbitration
table.
PCI Express VC extended
configuration registers 180h
to 18Ch
VC arbitration table
(see Section 5.27)
4-doubleword sized configuration registers that are the registered version of the
32-phase, WRR VC arbitration table. Each VC arbitration table entry is a 4-bit field.
3.4.4 128-Phase, WRR PCI Port Arbitration Timing
This section includes a timing diagram that illustrates the 128-phase, WRR time-based arbiter timing for the
bridge and 1394a OHCI devices. This timing diagram assumes aggressive mode since the transfer associated
with the bridge is stopped to start a 1394a OHCI transaction. The PCI bus cycle where the bridge is stopped
is indicated by the ‡ symbol. The bridge then waits until its next port arbitration table cycle to finish the transfer.
Bridge REQ
3
94a OHCI REQ
Bridge GNT
Isoc Ref
Clock
Port Arb
Table
PCI Bus
110000000111111100000001
Bridge
‡
1394a
OHCI
Bridge
1394a OHCI
GNT
Figure 3−4. Internal PCI Bus Timing
Not Recommended for New Designs