Datasheet

Feature/Protocol Descriptions
25
March 5 2007 − June 2011 SCPS154C
Table 3−6 identifies and describes the registers associated with 128-phase, WWR time-based arbitration
mode.
Table 3−6. 128-Phase, WRR Time-Based Arbiter Registers
REGISTER OFFSET REGISTER NAME DESCRIPTION
PCI Express VC extended
configuration registers 1C0h
to 1FCh
Port arbitration table (see
Section 5.28)
16-doubleword sized configuration registers that are the registered version of
the 128-phase, WRR port arbitration table. Each port arbitration table entry is
a 4-bit field.
PCI Express VC extended
configuration register 170h
VC1 resource control
(see Section 5.25)
Bits 19:17 (PORT_ARB_SELECT) equal to 100b define the port arbitration
mechanism as 128-phase WRR.
Bit 16 (LOAD_PORT_TABLE), when written with a 1b, transfers the port
arbitration table configuration register values to the internal registers used by
the PCI bus arbiter.
PCI Express VC extended
configuration register 176h
VC1 resource status
(see Section 5.26)
Bit 0 (PORT_TABLE_STATUS) equal to 1b indicates that the port arbitration
table configuration registers were updated but not loaded into the internal
arbitration table.
Device control memory
window register 04h
Upstream isochrony control
(see Section 6.4)
Bit 1 (PORTARB_LEVEL_1_EN) must be asserted to enable the 128-phase,
WRR time-based arbiter.
3.4.1.3 128-Phase, WRR Aggressive Time-Based Arbiter
The last option for PCI port arbitration is 128-phase, WRR aggressive time-based arbitration mode. This
arbitration mode performs the same as isochronous mode arbitration, but with one difference. When an
isochronous timing event occurs, the PCI bus arbiter deliberately stops a secondary bus master in the middle
of the transaction to assure that isochrony is preserved. The register setup for this arbitration option is the
same as the 128-phase, WRR time-based arbiter option with the following addition. Bit 2
(PORTARB_LEVEL_2_EN) in the device control memory window upstream isochrony control register at
offset 04h must be asserted (see Section 6.4).
3.4.2 PCI Isochronous Windows
The bridge has four separate windows that allow PCI bus-initiated memory transactions to be labeled with a
PCI Express traffic class (TC) beyond the default TC0. Each window designates a range of PCI memory space
that is mapped to a specified TC label. This advance feature is configured through the device control memory
window register map.
Table 3−7 identifies and describes the registers associated with isochronous arbitration mode.
Table 3−7. PCI Isochronous Windows
REGISTER OFFSET REGISTER NAME DESCRIPTION
Device control memory
window register 08h
Upstream isochronous window
0 control
(see Section 6.5)
Bit 0 (ISOC_WINDOW_EN) indicates that memory addresses within the
base and limit addresses are mapped to a specific traffic class ID.
Bits 3:1 (TC_ID) identify the specific traffic class ID.
Note: Memory-mapped register space exists for four upstream windows.
Only window 0 is included in this table.
Device control memory
window register 0Ch
Upstream isochronous window
0 base address
(see Section 6.6)
Window 0 base address
Device control memory
window register 10h
Upstream isochronous window
0 limit address
(see Section 6.7)
Window 0 limit address
Not Recommended for New Designs