Datasheet

Feature/Protocol Descriptions
23
March 5 2007 − June 2011 SCPS154C
Table 3−3. Messages Supported by the Bridge
MESSAGE SUPPORTED BRIDGE ACTION
Assert_INTx Yes Transmitted upstream
Deassert_INTx Yes Transmitted upstream
PM_Active_State_Nak Yes Received and processed
PM_PME Yes Transmitted upstream
PME_Turn_Off Yes Received and processed
PME_TO_Ack Yes Transmitted upstream
ERR_COR Yes Transmitted upstream
ERR_NONFATAL Yes Transmitted upstream
ERR_FATAL Yes Transmitted upstream
Set_Slot_Power_Limit Yes Received and processed
Unlock No Discarded
Hot plug messages No Discarded
Advanced switching messages No Discarded
Vendor defined type 0 No Unsupported request
Vendor defined type 1 No Discarded
All supported message transactions are processed per the PCI Express Base Specification.
3.4 Quality of Service and Isochronous Features
The bridge has both standard and advanced features that provide a robust solution for quality-of-service (QoS)
and isochronous applications. These features are best described by divided them into the following three
categories:
• PCI port arbitration. PCI port arbitration determines which bus master is granted the next transaction cycle
on the PCI bus. The three PCI port arbitration options are the classic PCI arbiter, the 128-phase, weighted
round-robin (WRR) time-based arbiter, and the 128-phase, WRR aggressive time-based arbiter. The
power-up register default is the classic PCI arbiter. The advanced time-based arbiter features are
provided to support isochronous applications.
• PCI isochronous windows. There are four separate windows that allow PCI bus-initiated memory
transactions to be labeled with a PCI Express traffic class (TC) beyond the default TC0. Each window
designates a range of PCI memory space that is mapped to a specified TC label. The power-up register
default is all four windows disabled.
• PCI Express extended VC with VC arbitration. With an extended VC, system software can map a particular
TC to a specific VC. The differentiated traffic on the second VC then uses dedicated system resources
to support a QoS environment. VC arbitration is provided to gate traffic to the upstream PCI Express link.
The three VC arbitration options include strict priority, hardware-fixed round-robin, and 32-phase WRR.
The power-up register default is strict priority with the second VC disabled.
When configuring these standard and advanced features, the following rules must be followed:
1. The default mode is classic PCI arbiter with the PCI isochronous windows disabled and the second VC
disabled. The bridge performs default PCI bus arbitration without any arbiter-related configuration register
setup.
2. If a second VC is enabled, then at least one PCI isochronous window must be configured to map upstream
transactions to the second VC.
3. If a second VC is enabled, then any VC arbiter option interacts with any PCI port arbiter option.
4. To enable the PCI isochronous windows it is not required to enable a second VC. The memory space to
traffic mapping always uses VC0 for all upstream traffic.
Not Recommended for New Designs