Datasheet

Feature/Protocol Descriptions
20
March 5 2007 − June 2011SCPS154C
3.1.2 Power-Down Sequence
1. Assert PERST to the device.
2. Remove the reference clock.
3. Remove 3.3-V and 1.5-V voltages.
Please see the power-down sequencing diagram in Figure 3−3. If the VDD_33_AUX terminal is to remain
powered after a system shutdown, then the bridge power-down sequence is exactly the same as shown in
Figure 3−3.
REFCLK
V
DD_15
V
DDA_15
V
DD_33
V
DDA_33
PERST
Figure 3−3. Power-Down Sequence
3.2 Bridge Reset Features
There are five bridge reset options that include internally-generated power-on reset, resets generated by
asserting input terminals, and software-initiated resets that are controlled by sending a PCI Express hot reset
or setting a configuration register bit. Table 3−1 identifies these reset sources and describes how the bridge
responds to each reset.
Not Recommended for New Designs