Datasheet

Feature/Protocol Descriptions
19
March 5 2007 − June 2011 SCPS154C
3.1.1 Power-Up Sequence
1. Assert PERST to the device.
2. Apply 1.5-V and 3.3-V voltages.
3. Apply a stable PCI Express reference clock.
4. To meet PCI Express specification requirements, PERST
cannot be deasserted until the following two
delay requirements are satisfied:
− Wait a minimum of 100 μs after applying a stable PCI Express reference clock. The 100-μs limit
satisfies the requirement for stable device clocks by the deassertion of PERST
.
− Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable
power by the deassertion of PERST
.
See the power-up sequencing diagram in Figure 3−2.
100 ms
100 s
REFCLK
V
DD_15
V
DDA_15
V
DD_33
V
DDA_33
PERST
Figure 3−2. Power-Up Sequence
Not Recommended for New Designs