Datasheet

Feature/Protocol Descriptions
18
March 5 2007 − June 2011SCPS154C
3 Feature/Protocol Descriptions
This chapter provides a high-level overview of all significant device features. Figure 3−1 shows a simplified
block diagram of the basic architecture of the PCI-Express to PCI Bridge with 1394a OHCI and two-port PHY.
The top of the diagram is the PCI Express interface and the 1394a OHCI with two-port PHY is located at the
bottom of the diagram.
PCI Express
Transmitter
PCI Express
Receiver
PCI Bus Interface
Configuration and
Memory Register
GPIO
Serial
EEPROM
Reset
Controller
Clock
Generator
Power
Mgmt
1394a OHCI with 2−Port PHY
1394
Cable
Port
1394
Cable
Port
Figure 3−1. XIO2200A Block Diagram
3.1 Power-Up/-Down Sequencing
The bridge contains both 1.5-V and 3.3-V power terminals. In addition, a V
AUX
supply exists to support the
D3
cold
state. The following power-up and power-down sequences describe how power is applied to these
terminals.
In addition, the bridge has three resets: PERST
, GRST, and an internal power-on reset. These resets are fully
described in Section 3.2. The following power-up and power-down sequences describe how PERST
is applied
to the bridge.
The application of the PCI Express reference clock (REFCLK) is important to the power-up/-down sequence
and is included in the following power-up and power-down descriptions.
Not Recommended for New Designs