Datasheet

Introduction
17
March 5 2007 − June 2011 SCPS154C
Table 2−11. Miscellaneous Terminals
SIGNAL
GGW/
ZGW
BALL #
ZHH
BALL #
I/O
TYPE
CELL
TYPE
CLAMP
RAIL
EXTERNAL
PARTS
DESCRIPTION
GPIO0 T05 P03 I/O
LV
CMOS
VDD_33 −
General-purpose I/O 0. This terminal functions as a GPIO
controlled by bit 0 (GPIO0_DIR) in the GPIO control
register (see Section 4.59).
Note: This terminal has an internal active pullup resistor.
GPIO1 U05 P04 I/O
LV
CMOS
VDD_33 −
General-purpose I/O 1. This terminal functions as a GPIO
controlled by bit 1 (GPIO1_DIR) in the GPIO control
register (see Section 4.59).
Note: This terminal has an internal active pullup resistor.
GPIO2 T06 N04 I/O
LV
CMOS
VDD_33 −
General-purpose I/O 2. This terminal functions as a GPIO
controlled by bit 2 (GPIO2_DIR) in the GPIO control
register (see Section 4.59).
Note: When PERST
is deasserted, this terminal must be
a 1b to enable the PCI Express 1.0a compatibility mode.
Note: This terminal has an internal active pullup resistor.
GPIO3 U06 M04 I/O
LV
CMOS
V
DD_33
−
General-purpose I/O 3. This terminal functions as a GPIO
controlled by bit 3 (GPIO3_DIR) in the GPIO control
register (see Section 4.59).
Note: This terminal has an internal active pullup resistor.
GPIO4 //
SCL
R07 P05 I/O
LV
CMOS
VDD_33
Optional
pullup
resistor
GPIO4 or serial-bus clock. This terminal functions as
serial-bus clock if a pullup resistor is detected on SDA. If
a pulldown resistor is detected on SDA, then this terminal
functions as GPIO4.
Note: In serial-bus mode, an external pullup resistor is
required to prevent the SCL signal from floating.
Note: This terminal has an internal active pullup resistor.
GPIO5 //
SDA
T07 N05 I/O
LV
CMOS
VDD_33
Pullup or
pulldown
resistor
GPIO5 or serial-bus data. This terminal functions as
serial-bus data if a pullup resistor is detected on SDA. If a
pulldown resistor is detected on SDA, then this terminal
functions as GPIO5.
Note: In serial-bus mode, an external pullup resistor is
required to prevent the SDA signal from floating.
GPIO6 U07 M05 I/O
LV
CMOS
VDD_33 −
General-purpose I/O 6. This terminal functions as a GPIO
controlled by bit 6 (GPIO6_DIR) in the GPIO control
register (see Section 4.59).
Note: This terminal has an internal active pullup resistor.
GPIO7 U08 L06 I/O
LV
CMOS
VDD_33 −
General-purpose I/O 7. This terminal functions as a GPIO
controlled by bit 7 (GPIO7_DIR) in the GPIO control
register (see Section 4.59).
Note: This terminal has an internal active pullup resistor.
GRST N17 L13 I
LV
CMOS
VDD_33_
COMBIO
−
Global reset input. Asynchronously resets all logic in
device, including sticky bits and power management state
machines.
Note: The GRST
input buffer has both hysteresis and an
internal active pullup.
Not Recommended for New Designs