Datasheet
Introduction
14
March 5 2007 − June 2011SCPS154C
Table 2−7. PCI Express Terminals
SIGNAL
GGW/
ZGW
BALL #
ZHH
BALL #
I/O
TYPE
CELL
TYPE
CLAMP
RAIL
EXTERNAL
PARTS
DESCRIPTION
PERST J17 H12 I
LV
CMOS
VDD_33_
COMBIO
−
PCI Express reset input. The PERST signal identifies
when the system power is stable and generates an
internal power-on reset.
Note: The PERST
input buffer has hysteresis.
REF0_PCIE
REF1_PCIE
L16
L17
J14
J13
I/O BIAS −
External
resistor
External reference resistor + and − terminals for
setting TX driver current. An external resistor is
connected between terminals L16 and L17.
RXP
RXN
E17
E16
E14
E13
DI
HS
DIFF IN
VDD_15 −
High-speed receive pair. RXP and RXN comprise the
differential receive pair for the single PCI Express lane
supported.
TXP
TXN
H17
H16
G14
G13
DO
HS
DIFF
OUT
VSS
Series
capacitors
High-speed transmit pair. TXP and TXN comprise the
differential transmit pair for the single PCI Express
lane supported.
WAKE M16 K14 O
LV
CMOS
VDD_33_
COMBIO
−
Wake is an active low signal that is driven low to
reactivate the PCI Express link hierarchy’s main power
rails and reference clocks.
Note: Since WAKE
is an open-drain output buffer, a
system side pullup resistor is required.
Table 2−8. Clock Terminals
SIGNAL
GGW/
ZGW
BALL #
ZHH
BALL #
I/O
TYPE
CELL
TYPE
CLAMP
RAIL
EXTERNAL
PARTS
DESCRIPTION
REFCLK_SEL A16 A14 I
LV
CMOS
VDD_33
Pullup or
pulldown
resistor
Reference clock select. This terminal selects the
reference clock input.
0 = 100-MHz differential common reference clock
used
1 = 125-MHz single-ended reference clock used
REFCLK+ C17 C13 DI
HS
DIFF
IN
VDD_33 −
Reference clock. REFCLK+ and REFCLK− comprise
the differential input pair for the 100-MHz system
reference clock. For a single-ended, 125-MHz system
reference clock, use the REFCLK+ input.
REFCLK− C16 C14 DI
HS
DIFF
IN
VDD_33
Capacitor to
VSS for
single-ended
mode
Reference clock. REFCLK+ and REFCLK− comprise
the differential input pair for the 100-MHz system
reference clock. For a single-ended, 125-MHz system
reference clock, attach a capacitor from REFCLK− to
VSS.
Not Recommended for New Designs