Datasheet

1394 OHCI Memory-Mapped TI Extension Register Space
168
March 5 2007 − June 2011SCPS154C
Table 9−3. Link Enhancement Register Description (Continued)
BIT FIELD NAME TYPE DESCRIPTION
13−12† atx_thresh RW
This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the OHCI
controller retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward operation.
00 = Threshold ~ 2K bytes resulting in a store-and-forward operation
01 = Threshold ~ 1.7K bytes (default)
10 = Threshold ~ 1K bytes
11 = Threshold ~ 512 bytes
These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K-byte
threshold is optimal. Changing this value may increase or decrease the 1394 latency depending on the
average PCI bus latency.
Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds
or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than
the AT threshold, then the remaining data must be received before the AT FIFO is emptied; otherwise,
an underrun condition occurs, resulting in a packet error at the receiving node. As a result, the link then
commences store-and-forward operation. Wait until it has the complete packet in the FIFO before
retransmitting it on the second attempt to ensure delivery.
An AT threshold of 2K results in store-and-forward operation, which means that asynchronous data will
not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 2K
results in only complete packets being transmitted.
Note that the OHCI controller will always use store-and-forward when the asynchronous transmit
retries register at OHCI offset 08h (see Section 8.3, Asynchronous Transmit Retries Register) is
cleared.
11 RSVD R Reserved. Bit 11 returns 0b when read.
10† enab_mpeg_ts RW
Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1b, the enhancement is enabled for
MPEG CIP transmit streams (FMT = 20h). The default value for this bit is 0b.
9 RSVD R Reserved. Bit 9 returns 0b when read.
8† enab_dv_ts RW
Enable DV CIP timestamp enhancement. When bit 8 is set to 1b, the enhancement is enabled for DV
CIP transmit streams (FMT = 00h). The default value for this bit is 0b.
7† enab_unfair RW
Enable asynchronous priority requests. OHCI-Lynx™ compatible. Setting bit 7 to 1b enables the link
to respond to requests with priority arbitration. It is recommended that this bit be set to 1b. The default
value for this bit is 0b.
6−3 RSVD R Reserved. Bits 6−3 return 0h when read.
2† RSVD RW Reserved. Bit 2 defaults to 0b and must remain 0b for normal operation of the OHCI core.
1† enab_accel RW
Enable acceleration enhancements. OHCI-Lynx™ compatible. When bit 1 is set to 1b, the PHY layer
is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is,
ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1b. The default
value for this bit is 0b.
0 RSVD R Reserved. Bit 0 returns 0b when read.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Not Recommended for New Designs