Datasheet

1394 OHCI Memory-Mapped TI Extension Register Space
167
March 5 2007 − June 2011 SCPS154C
Table 9−2. Isochronous Receive Digital Video Enhancements Register Description (Continued)
BIT FIELD NAME TYPE DESCRIPTION
5 DV_Branch1 RSC When bit 5 is set to 1b, the isochronous receive context 1 synchronizes reception to the DV frame start
tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if
a DV frame start tag is received out of place. This bit is only interpreted when bit 4 (CIP_Strip1) is set
to 1b and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset
420h/424h (see Section 8.44) is cleared to 0b.
4 CIP_Strip1 RSC When bit 4 is set to 1b, the isochronous receive context 1 strips the first two quadlets of payload. This
bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 420h/424h (see Section 8.44) is cleared to 0b.
3−2 RSVD R Reserved. Bits 3 and 2 return 00b when read.
1 DV_Branch0 RSC When bit 1 is set to 1b, the isochronous receive context 0 synchronizes reception to the DV frame start
tag in bufferfill mode if input_more.b = 01b and jumps to the descriptor pointed to by frameBranch if
a DV frame start tag is received out of place. This bit is only interpreted when bit 0 (CIP_Strip0) is set
to 1b and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset
400h/404h (see Section 8.44) is cleared to 0b.
0 CIP_Strip0 RSC When bit 0 is set to 1b, the isochronous receive context 0 strips the first two quadlets of payload. This
bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 400h/404h (see Section 8.44) is cleared to 0b.
9.4 Link Enhancement Register
This register is a memory-mapped set/clear register that is an alias of the link enhancement control register
at PCI offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial
EEPROM, if one is present, as noted in the bit descriptions below. If the bits are to be initialized by software,
then the bits must be initialized prior to setting bit 19 (LPS) in the host controller control register at OHCI offset
50h/54h (see Section 8.16). See Table 9−3 for a complete description of the register contents.
TI extension register offset: A88h set register
A8Ch clear register
Register type: Read/Set/Clear, Read-only
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Table 9−3. Link Enhancement Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−16 RSVD R Reserved. Bits 31−16 return 0000h when read.
15† dis_at_pipeline RW
Disable AT pipelining. When bit 15 is set to 1b, out-of-order AT pipelining is disabled. The default value
for this bit is 0b.
14† RSVD RW Reserved. Bit 14 defaults to 0b and must remain 0b for normal operation of the OHCI core.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Not Recommended for New Designs