Datasheet

1394 OHCI Memory-Mapped Register Space
163
March 5 2007 − June 2011 SCPS154C
Table 8−34. Isochronous Receive Context Control Register Description (Continued)
BIT FIELD NAME TYPE DESCRIPTION
28 multiChanMode RSC When bit 28 is set to 1b, the corresponding isochronous receive DMA context receives packets for
all isochronous channels enabled in the isochronous receive channel mask high register at OHCI
offset 70h/74h (see Section 8.19) and isochronous receive channel mask low register at OHCI offset
78h/7Ch (see Section 8.20). The isochronous channel number specified in the isochronous receive
context match register (see Section 8.46) is ignored.
When this bit is cleared, the isochronous receive DMA context receives packets for the single
channel specified in the isochronous receive context match register (see Section 8.46). Only one
isochronous receive DMA context may use the isochronous receive channel mask registers (see
Sections 8.19, and 8.20). If more than one isochronous receive context control register has this bit
set, then the results are undefined. The value of this bit must not be changed while bit 10 (active)
or bit 15 (run) is set to 1b.
27 dualBufferMode RSC When bit 27 is set to 1b, receive packets are separated into first and second payload and streamed
independently to the firstBuffer series and secondBuffer series as described in Section 10.2.3 in the
1394 Open Host Controller Interface Specification. Also, when bit 27 is set to 1b, both bits 28
(multiChanMode) and 31 (bufferFill) are cleared to 00b. The value of this bit does not change when
either bit 10 (active) or bit 15 (run) is set to 1b.
26−16 RSVD R Reserved. Bits 26−16 return 000 0000 0000b when read.
15 run RSCU Bit 15 is set to 1b by software to enable descriptor processing for the context and cleared by software
to stop descriptor processing. The controller changes this bit only on a system (hardware) or
software reset.
14−13 RSVD R Reserved. Bits 14 and 13 return 00b when read.
12 wake RSU Software sets bit 12 to 1b to cause the controller to continue or resume descriptor processing. The
controller clears this bit on every descriptor fetch.
11 dead RU The controller sets bit 11 to 1b when it encounters a fatal error, and clears the bit when software
clears bit 15 (run).
10 active RU The controller sets bit 10 to 1b when it is processing descriptors.
9−8 RSVD R Reserved. Bits 9 and 8 return 00b when read.
7−5 spd RU This field indicates the speed at which the packet was received.
000 = 100M bits/s
001 = 200M bits/s
010 = 400M bits/s
All other values are reserved.
4−0 event code RU For bufferFill mode, possible values are: ack_complete, evt_descriptor_read, evt_data_write, and
evt_unknown. Packets with data errors (either dataLength mismatches or dataCRC errors) and
packets for which a FIFO overrun occurred are backed out. For packet-per-buffer mode, possible
values are: ack_complete, ack_data_error, evt_long_packet, evt_overrun, evt_descriptor_read,
evt_data_write, and evt_unknown.
8.45 Isochronous Receive Context Command Pointer Register
The isochronous receive context command pointer register contains a pointer to the address of the first
descriptor block that the controller accesses when software enables an isochronous receive context by setting
bit 15 (run) in the isochronous receive context control register (see Section 8.44) to 1b. The n value in the
following register addresses indicates the context number (n = 0, 1, 2, 3).
OHCI register offset: 40Ch + (32 * n)
Register type: Read-only
Default value: XXXX XXXXh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE X X X X X X X X X X X X X X X X
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE X X X X X X X X X X X X X X X X
Not Recommended for New Designs