Datasheet

1394 OHCI Memory-Mapped Register Space
145
March 5 2007 − June 2011 SCPS154C
Table 8−16. Interrupt Mask Register Description (Continued)
BIT FIELD NAME TYPE DESCRIPTION
15 selfIDcomplete2 RSC When this bit and bit 15 (selfIDcomplete2) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this second-self-ID-complete interrupt mask enables interrupt generation.
14−10 RSVD R Reserved. Bits 14−10 return 00000b when read.
9 lockRespErr RSC When this bit and bit 9 (lockRespErr) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this lock-response-error interrupt mask enables interrupt generation.
8 postedWriteErr RSC When this bit and bit 8 (postedWriteErr) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this posted-write-error interrupt mask enables interrupt generation.
7 isochRx RSC When this bit and bit 7 (isochRx) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this isochronous-receive-DMA interrupt mask enables interrupt
generation.
6 isochTx RSC When this bit and bit 6 (isochTx) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this isochronous-transmit-DMA interrupt mask enables interrupt
generation.
5 RSPkt RSC When this bit and bit 5 (RSPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21)
are set to 11b, this receive-response-packet interrupt mask enables interrupt generation.
4 RQPkt RSC When this bit and bit 4 (RQPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21)
are set to 11b, this receive-request-packet interrupt mask enables interrupt generation.
3 ARRS RSC When this bit and bit 3 (ARRS) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21)
are set to 11b, this asynchronous-receive-response-DMA interrupt mask enables interrupt generation.
2 ARRQ RSC When this bit and bit 2 (ARRQ) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21)
are set to 11b, this asynchronous-receive-request-DMA interrupt mask enables interrupt generation.
1 respTxComplete RSC When this bit and bit 1 (respTxComplete) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this response-transmit-complete interrupt mask enables interrupt
generation.
0 reqTxComplete RSC When this bit and bit 0 (reqTxComplete) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this request-transmit-complete interrupt mask enables interrupt
generation.
Not Recommended for New Designs