Datasheet

1394 OHCI Memory-Mapped Register Space
144
March 5 2007 − June 2011SCPS154C
8.22 Interrupt Mask Register
The interrupt mask set/clear register enables the various interrupt sources. Reads from either the set register
or the clear register always return the contents of the interrupt mask register. In all cases except
masterIntEnable (bit 31) and vendorSpecific (bit 30), the enables for each interrupt event align with the
interrupt event register bits detailed in Table 8−15.
This register is fully compliant with the 1394 Open Host Controller Interface Specification and the controller
adds an interrupt function to bit 30. See Table 8−16 for a complete description of bits 31 and 30.
OHCI register offset: 88h set register
8Ch clear register
Register type: Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only
Default value: XXXX 0XXXh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE X X 0 0 0 X X X X X X X X 0 X X
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 X X X X X X X X X X
Table 8−16. Interrupt Mask Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 masterIntEnable RSCU Master interrupt enable. If bit 31 is set to 1b, then external interrupts are generated in accordance with
the interrupt mask register. If this bit is cleared, then external interrupts are not generated regardless
of the interrupt mask register settings.
30 VendorSpecific RSC When this bit and bit 30 (vendorSpecific) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this vendor-specific interrupt mask enables interrupt generation.
29 SoftInterrupt RSC When this bit and bit 29 (SoftInterrupt) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this soft-interrupt mask enables interrupt generation.
28 RSVD R Reserved. Bit 28 returns 0b when read.
27 ack_tardy RSC When this bit and bit 27 (ack_tardy) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this acknowledge-tardy interrupt mask enables interrupt generation.
26 phyRegRcvd RSC When this bit and bit 26 (phyRegRcvd) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this PHY-register interrupt mask enables interrupt generation.
25 cycleTooLong RSC When this bit and bit 25 (cycleTooLong) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this cycle-too-long interrupt mask enables interrupt generation.
24 unrecoverableError RSC When this bit and bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this unrecoverable-error interrupt mask enables interrupt generation.
23 cycleInconsistent RSC When this bit and bit 23 (cycleInconsistent) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this inconsistent-cycle interrupt mask enables interrupt generation.
22 cycleLost RSC When this bit and bit 22 (cycleLost) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this lost-cycle interrupt mask enables interrupt generation.
21 cycle64Seconds RSC When this bit and bit 21 (cycle64Seconds) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this 64-second-cycle interrupt mask enables interrupt generation.
20 cycleSynch RSC When this bit and bit 20 (cycleSynch) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this isochronous-cycle interrupt mask enables interrupt generation.
19 phy RSC When this bit and bit 19 (phy) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21)
are set to 11b, this PHY-status-transfer interrupt mask enables interrupt generation.
18 regAccessFail RSC When this bit and bit 18 (regAccessFail) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this register-access-failed interrupt mask enables interrupt generation.
17 busReset RSC When this bit and bit 17 (busReset) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this bus-reset interrupt mask enables interrupt generation.
16 selfIDcomplete RSC When this bit and bit 16 (selfIDcomplete) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this self-ID-complete interrupt mask enables interrupt generation.
Not Recommended for New Designs