Datasheet

1394 OHCI Memory-Mapped Register Space

141

March 5 2007 − June 2011 SCPS154C

8.20 Isochronous Receive Channel Mask Low Register

The isochronous receive channel mask low set/clear register enables packet receives from the lower 32

isochronous data channels. See Table 8−14 for a complete description of the register contents.

OHCI register offset: 78h set register

7Ch clear register

Default value: XXXX XXXXh

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE X X X X X X X X X X X X X X X X

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE X X X X X X X X X X X X X X X X

Table 8−14. Isochronous Receive Channel Mask Low Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 isoChannel31 RSC When bit 31 is set to 1b, the controller is enabled to receive from isochronous channel number 31.

30 isoChannel30 RSC When bit 30 is set to 1b, the controller is enabled to receive from isochronous channel number 30.

29−2 isoChanneln RSC Bits 29 through 2 (isoChanneln, where n = 29, 28, 27, …, 2) follow the same pattern as bits 31 and 30.

1 isoChannel1 RSC When bit 1 is set to 1b, the controller is enabled to receive from isochronous channel number 1.

0 isoChannel0 RSC When bit 0 is set to 1b, the controller is enabled to receive from isochronous channel number 0.

Not Recommended for New Designs