Datasheet

1394 OHCI Memory-Mapped Register Space
139
March 5 2007 − June 2011 SCPS154C
8.18 Self-ID Count Register
The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags
self-ID packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 8−12 for a complete
description of the register contents.
OHCI register offset: 68h
Register type: Read/Update, Read-only
Default value: X0XX 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE X 0 0 0 0 0 0 0 X X X X X X X X
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 8−12. Self-ID Count Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 selfIDError RU When bit 31 is set to 1b, an error was detected during the most recent self-ID packet reception. The
contents of the self-ID buffer are undefined. This bit is cleared after a self-ID reception in which no
errors are detected. Note that an error can be a hardware error or a host bus write error.
30−24 RSVD R Reserved. Bits 30−24 return 000 0000b when read.
23−16 selfIDGeneration RU The value in this field increments each time a bus reset is detected. This field rolls over to 0 after
reaching 255.
15−11 RSVD R Reserved. Bits 15−11 return 00000b when read.
10−2 selfIDSize RU This field indicates the number of quadlets that have been written into the self-ID buffer for the current
bits 23−16 (selfIDGeneration field). This includes the header quadlet and the self-ID data. This field
is cleared to 0 0000 0000b when the self-ID reception begins.
1−0 RSVD R Reserved. Bits 1 and 0 return 00b when read.
Not Recommended for New Designs