Datasheet

1394 OHCI Memory-Mapped Register Space
133
March 5 2007 − June 2011 SCPS154C
8.7 Configuration ROM Header Register
The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM,
offset FFFF F000 0400h. See Table 8−6 for a complete description of the register contents.
OHCI register offset: 18h
Register type: Read/Write
Default value: 0000 XXXXh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE X X X X X X X X X X X X X X X X
Table 8−6. Configuration ROM Header Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−24 info_length RW IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control
register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. The default value for this field is 0h.
23−16 crc_length RW IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control
register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. The default value for this field is 0h.
15−0 rom_crc_value RW IEEE 1394 bus-management field. Must be valid at any time bit 17 (linkEnable) in the host controller
control register at OHCI offset 50h/54h (see Section 8.16) is set to 1b.
8.8 Bus Identification Register
The bus identification register externally maps to the first quadlet in the Bus_Info_Block and contains the
constant 3133 3934h, which is the ASCII value of 1394.
OHCI register offset: 1Ch
Register type: Read-only
Default value: 3133 3934h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 1 1 1 0 0 1 0 0 1 1 0 1 0 0
Not Recommended for New Designs