Datasheet

1394 OHCI Memory-Mapped Register Space

132

March 5 2007 − June 2011SCPS154C

8.5 CSR Compare Register

The CSR compare register accesses the bus management CSR registers from the host through

compare-swap operations. This register contains the data to be compared with the existing value of the CSR

resource.

OHCI register offset: 10h

Default value: XXXX XXXXh

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE X X X X X X X X X X X X X X X X

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE X X X X X X X X X X X X X X X X

8.6 CSR Control Register

The CSR control register accesses the bus management CSR registers from the host through compare-swap

operations. This register controls the compare-swap operation and selects the CSR resource. See Table 8−5

for a complete description of the register contents.

OHCI register offset: 14h

Default value: 8000 000Xh

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X

Table 8−5. CSR Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 csrDone RU Bit 31 is set to 1b by the controller when a compare-swap operation is complete. It is cleared whenever

this register is written.

30−2 RSVD R Reserved. Bits 30−2 return 0 0000 0000 0000 0000 0000 0000 0000b when read.

1−0 csrSel RW This field selects the CSR resource as follows:

00 = BUS_MANAGER_ID

01 = BANDWIDTH_AVAILABLE

10 = CHANNELS_AVAILABLE_HI

11 = CHANNELS_AVAILABLE_LO

Not Recommended for New Designs