Datasheet

1394 OHCI Memory-Mapped Register Space
129
March 5 2007 − June 2011 SCPS154C
Table 8−1. OHCI Register Map (Continued)
DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET
Asynchronous context control
ContextControlSet 1C0h
Asynchronous
Asynchronous context control
ContextControlClear 1C4h
Asynchronous
Request Receive
Reserved — 1C8h
Request Receive
[ ARRQ ] Asynchronous context command pointer CommandPtr 1CCh
[Q]
Reserved — 1D0h−1DCh
Asynchronous context control
ContextControlSet 1E0h
Asynchronous
Asynchronous context control
ContextControlClear 1E4h
Asynchronous
Response Receive
Reserved — 1E8h
Response Receive
[ ARRS ] Asynchronous context command pointer CommandPtr 1ECh
[]
Reserved — 1F0h−1FCh
Isochronous transmit context control
ContextControlSet 200h + 16*n
Isochronous
Isochronous transmit context control
ContextControlClear 204h + 16*n
Isochronous
Transmit Context n
Reserved — 208h + 16*n
Transmit Context n
n = 0, 1, 2, 3, …, 7 Isochronous transmit context command pointer CommandPtr 20Ch + 16*n
,,,, ,
Reserved — 210h−3FCh
Isochronous receive context control
ContextControlSet 400h + 32*n
Isochronous
Isochronous receive context control
ContextControlClear 404h + 32*n
Isochronous
Receive Context n
Reserved — 408h + 32*n
Receive Context n
n = 0, 1, 2, 3 Isochronous receive context command pointer CommandPtr 40Ch + 32*n
,,,
Isochronous receive context match ContextMatch 410h + 32*n
8.1 OHCI Version Register
The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is
present. See Table 8−2 for a complete description of the register contents.
OHCI register offset: 00h
Register type: Read-only
Default value: 0X01 0010h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 1
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Table 8−2. OHCI Version Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−25 RSVD R Reserved. Bits 31−25 return 000 0000b when read.
24† GUID_ROM RU The controller sets bit 24 to 1b if the serial EEPROM is detected. If the serial EEPROM is present, then the
Bus_Info_Block is automatically loaded on system (hardware) reset. The default value for this bit is 0b.
23−16 version R Major version of the OHCI. The controller is compliant with the 1394 Open Host Controller Interface
Specification (Release 1.1); thus, this field reads 01h.
15−8 RSVD R Reserved. Bits 15−8 return 00h when read.
7−0 revision R Minor version of the OHCI. The controller is compliant with the 1394 Open Host Controller Interface
Specification (Release 1.1); thus, this field reads 10h.
†
One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Not Recommended for New Designs