Datasheet

1394 OHCI Memory-Mapped Register Space
128
March 5 2007 − June 2011SCPS154C
Table 8−1. OHCI Register Map (Continued)
DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET
—
Interrupt event
IntEventSet 80h
Interrupt event
IntEventClear 84h
Interrupt mask
IntMaskSet 88h
Interrupt mask
IntMaskClear 8Ch
Isochronous transmit interrupt event
IsoXmitIntEventSet 90h
Isochronous transmit interrupt event
IsoXmitIntEventClear 94h
Isochronous transmit interrupt mask
IsoXmitIntMaskSet 98h
Isochronous transmit interrupt mask
IsoXmitIntMaskClear 9Ch
—
Isochronous receive interrupt event
IsoRecvIntEventSet A0h
Isochronous receive interrupt event
IsoRecvIntEventClear A4h
Isochronous receive interrupt mask
IsoRecvIntMaskSet A8h
Isochronous receive interrupt mask
IsoRecvIntMaskClear ACh
Initial bandwidth available InitialBandwidthAvailable B0h
Initial channels available high InitialChannelsAvailableHi B4h
Initial channels available low InitialChannelsAvailableLo B8h
Reserved — BCh−D8h
Fairness control FairnessControl DCh
Link control †
LinkControlSet E0h
Link control †
LinkControlClear E4h
Node identification NodeID E8h
PHY layer control PhyControl ECh
Isochronous cycle timer Isocyctimer F0h
Reserved — F4h−FCh
Asynchronous request filter high
AsyncRequestFilterHiSet 100h
Asynchronous request filter high
AsyncRequestFilterHiClear 104h
Asynchronous request filter low
AsyncRequestFilterLoSet 108h
Asynchronous request filter low
AsyncRequestFilterLoClear 10Ch
Physical request filter high
PhysicalRequestFilterHiSet 110h
Physical request filter high
PhysicalRequestFilterHiClear 114h
Physical request filter low
PhysicalRequestFilterLoSet 118h
Physical request filter low
PhysicalRequestFilterLoClear 11Ch
Physical upper bound PhysicalUpperBound 120h
Reserved — 124h−17Ch
Asynchronous context control
ContextControlSet 180h
Asynchronous
Asynchronous context control
ContextControlClear 184h
Asynchronous
Request Transmit
Reserved — 188h
Request Transmit
[ ATRQ ] Asynchronous context command pointer CommandPtr 18Ch
[Q]
Reserved — 190h−19Ch
Asynchronous context control
ContextControlSet 1A0h
Asynchronous
Asynchronous context control
ContextControlClear 1A4h
Asynchronous
Response Transmit
Reserved — 1A8h
Response Transmit
[ ATRS ] Asynchronous context command pointer CommandPtr 1ACh
[]
Reserved — 1B0h−1BCh
†
One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Not Recommended for New Designs