Datasheet

1394 OHCI Memory-Mapped Register Space
127
March 5 2007 − June 2011 SCPS154C
8 1394 OHCI Memory-Mapped Register Space
The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped
into a 2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration
space (see Section 7.8). These registers are the primary interface for controlling the IEEE 1394 link function.
This section provides the register interface and bit descriptions. Several set/clear register pairs in this
programming model are implemented to solve various issues with typical read-modify-write control registers.
There are two addresses for a set/clear register: RegisterSet and RegisterClear. See Table 8−1 for a register
listing. A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set to 1b; a
0 bit leaves the corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit
in the set/clear register to be cleared; a 0 bit leaves the corresponding bit in the set/clear register unaffected.
Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register,
respectively. However, sometimes reading the RegisterClear provides a masked version of the set or clear
register. The interrupt event register is an example of this behavior.
Table 8−1. OHCI Register Map
DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET
— OHCI version Version 00h
GUID ROM GUID_ROM 04h
Asynchronous transmit retries ATRetries 08h
CSR data CSRData 0Ch
CSR compare CSRCompareData 10h
CSR control CSRControl 14h
Configuration ROM header ConfigROMhdr 18h
Bus identification BusID 1Ch
Bus options † BusOptions 20h
GUID high † GUIDHi 24h
GUID low † GUIDLo 28h
Reserved — 2Ch−30h
Configuration ROM mapping ConfigROMmap 34h
Posted write address low PostedWriteAddressLo 38h
Posted write address high PostedWriteAddressHi 3Ch
Vendor ID VendorID 40h
Reserved — 44h−4Ch
Host controller control †
HCControlSet 50h
Host controller control †
HCControlClr 54h
Reserved — 58h−5Ch
Self-ID Reserved — 60h
Self-ID buffer pointer SelfIDBuffer 64h
Self-ID count SelfIDCount 68h
Reserved — 6Ch
—
Isochronous receive channel mask high
IRChannelMaskHiSet 70h
Isochronous receive channel mask high
IRChannelMaskHiClear 74h
Isochronous receive channel mask low
IRChannelMaskLoSet 78h
Isochronous receive channel mask low
IRChannelMaskLoClear 7Ch
†
One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Not Recommended for New Designs