Datasheet

1394 OHCI—PCI Configuration Space
126
March 5 2007 − June 2011SCPS154C
Table 7−19. Link Enhancement Control Register Description (Continued)
BIT FIELD NAME TYPE DESCRIPTION
11 RSVD R Reserved. Bit 11 returns 0b when read.
10† enab_mpeg_ts RW
Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1b, the enhancement is enabled for
MPEG CIP transmit streams (FMT = 20h). The default value for this bit is 0b.
9 RSVD R Reserved. Bit 9 returns 0b when read.
8† enab_dv_ts RW
Enable DV CIP timestamp enhancement. When bit 8 is set to 1b, the enhancement is enabled for DV
CIP transmit streams (FMT = 00h). The default value for this bit is 0b.
7† enab_unfair RW
Enable asynchronous priority requests. OHCI-Lynx™ compatible. Setting bit 7 to 1b enables the link
to respond to requests with priority arbitration. It is recommended that this bit be set to 1b. The default
value for this bit is 0b.
6−3 RSVD R Reserved. Bits 6−3 return 0h when read.
2† RSVD RW Reserved. Bit 2 defaults to 0b and must remain 0b for normal operation of the OHCI core.
1† enab_accel RW
Enable acceleration enhancements. OHCI-Lynx™ compatible. When bit 1 is set to 1b, the PHY layer
is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is,
ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1b. The default
value for this bit is 0b.
0 RSVD R Reserved. Bit 0 returns 0b when read.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
7.24 Subsystem Access Register
Write access to the subsystem access register updates the subsystem identification registers identically to
OHCI-Lynx™. The system ID value written to this register may also be read back from this register. See
Table 7−20 for a complete description of the register contents.
PCI register offset: F8h
Register type: Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 7−20. Subsystem Access Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−16† SUBDEV_ID RW Subsystem device ID alias. This field indicates the subsystem device ID.
15−0† SUBVEN_ID RW Subsystem vendor ID alias. This field indicates the subsystem vendor ID.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
7.25 TI Proprietary Register
This read-only TI proprietary register is located at offset E2h. The default state is 0000 0000h.
PCI register offset: FCh
Register type: Read-only
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Not Recommended for New Designs