Datasheet

1394 OHCI—PCI Configuration Space
124
March 5 2007 − June 2011SCPS154C
7.22 PCI Miscellaneous Configuration Register
The PCI miscellaneous configuration register provides miscellaneous PCI-related configuration. See
Table 7−18 for a complete description of the register contents.
PCI register offset: F0h
Register type: Read/Write, Read-only
Default value: 0000 0800h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
Table 7−18. Miscellaneous Configuration Register
BIT FIELD NAME TYPE DESCRIPTION
31−16 RSVD R Reserved. Bits 31−16 return 0000h when read.
15 PME_D3COLD R
PME support from D3
cold
. The 1394a OHCI core does not support PME generation from D3
cold
.
Therefore, this bit is tied to 0b.
14−12 RSVD R Reserved. Bits 14−12 return 000b when read.
11 PCI2_3_EN R
PCI 2.3 enable. The 1394 OHCI core always conforms to the PCI 2.3 specification; therefore, this bit
is tied to 1b.
10
IGNORE_
MSTRINT_
ENA_FOR_PME
RW
IGNORE_MSTRINT_ENA_FOR_PME bit for PME generation. When set, this bit causes bit 26 of the
OHCI vendor ID register (OHCI offset 40h, see Section 8.15) to read 1b. Otherwise, bit 26 reads 0b.
0 = PME
behavior generated from unmasked interrupt bits and IntMask.masterIntEnable bit
(default)
1 = PME
generation does not depend on the value of IntMask.masterIntEnable
9−8† MR_ENHANCE RW
This field selects the read command behavior of the PCI master for read transactions of greater than
two data phases. For read transactions of one or two data phases, a memory read command is used.
00 = Memory read line (default)
01 = Memory read
10 = Memory read multiple
11 = Reserved, behavior reverts to default
7†
PCI_PM_
VERSION_CTRL
RW
PCI power management version control. This bit controls the value reported in the Version field of the
power management capabilities register of the 1394 OHCI function.
0 = Version fields report 010b for Power Management 1.1 compliance (default)
1 = Version fields report 011b for Power Management 1.2 compliance
6−5 RSVD R Reserved. Bits 6−5 return 00b when read.
4† DIS_TGT_ABT RW
Disable target abort. Bit 4 controls the no-target-abort mode, in which the OHCI controller returns
indeterminate data instead of signaling target abort. The OHCI LLC is divided into the PCLK and
SCLK domains. If software tries to access registers in the link that are not active because the
SCLK is disabled, then a target abort is issued by the link. On some systems, this can cause a
problem resulting in a fatal system error. Enabling this bit allows the link to respond to these types
of requests by returning FFh.
0 = Responds with OHCI-Lynx™ compatible target abort (default)
1 = Responds with indeterminate data equal to FFh. It is recommended that this bit be set to 1b
3† SB_EN RW
Serial bus enable. In the bridge, the serial bus interface is controlled using the bridge configuration
registers. Therefore, this bit has no effect in the 1394a OHCI function. The default value for this bit is
0b.
2†
DISABLE_
SCLKGATE
RW
Disable SCLK test feature. This bit controls locking or unlocking the SCLK to the 1394a OHCI core
PCI bus clock input. This is a test feature only and must be cleared to 0b (all applications).
0 = Hardware decides auto-gating of the PHY clock (default)
1 = Disables auto-gating of the PHY clock
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Not Recommended for New Designs