Datasheet

1394 OHCI—PCI Configuration Space
123
March 5 2007 − June 2011 SCPS154C
7.21 PCI PHY Control Register
The PCI PHY control register provides a method for enabling the PHY CNA output. See Table 7−17 for a
complete description of the register contents.
PCI register offset: ECh
Register type: Read/Write, Read-only
Default value: 0000 0008h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Table 7−17. PCI PHY Control Register
BIT FIELD NAME TYPE DESCRIPTION
31−8 RSVD R Reserved. Bits 31−8 return 00 0000h when read.
7† CNAOUT RW When bit 7 is set to 1b, the PHY CNA output is routed to terminal U09. When implementing a serial
EEPROM, this bit can be set by programming bit 7 of offset 38h in the EEPROM to 1.
6−5 RSVD R Reserved. Bits 6−5 return 00b when read.
4† RSVD RW Reserved. Bit 4 defaults to 0b and must remain 0b for normal operation of the PHY.
3† RSVD RW Reserved. Bit 3 defaults to 1b to indicate compliance with IEEE Std 1394a-2000. If a serial
EEPROM is implemented, then bit 3 at EEPROM byte offset 38h must be set to 1. See Table 3−10,
EEPROM Register Loading Map.
2† RSVD RW Reserved. Bit 2 defaults to 0b and must remain 0b for normal operation of the PHY.
1† RSVD RW Reserved. Bit 1 defaults to 0b and must remain 0b for normal operation of the PHY. If a serial
EEPROM is implemented, then bit 1 at EEPROM byte offset 38h must be set to 0. See Table 3−10,
EEPROM Register Loading Map.
0† RSVD RW Reserved. Bit 0 defaults to 0b and must remain 0b for normal operation of the PHY.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Not Recommended for New Designs