Datasheet

1394 OHCI—PCI Configuration Space
122
March 5 2007 − June 2011SCPS154C
7.19 Power Management Control and Status Register
The power management control and status register implements the control and status of the PCI power
management function. This register is not affected by the internally-generated reset caused by the transition
from the D3
hot
to D0 state. See Table 7−15 for a complete description of the register contents.
PCI register offset: 48h
Register type: Read/Write, Read-only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 7−15. Power Management Control and Status Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 PME_STS R This bit returns 0b, because PME is not supported.
14−13 DATA_SCALE R This field returns 00b, because the data register is not implemented.
12−9 DATA_SELECT R This field returns 0h, because the data register is not implemented.
8 PME_ENB R This bit returns 0b, because PME is not supported.
7−2 RSVD R Reserved. Bits 7−2 return 00 0000b when read.
1−0† PWR_STATE RW Power state. This 2-bit field sets the OHCI controller power state and is encoded as follows:
00 = Current power state is D0 (default)
01 = Current power state is D1
10 = Current power state is D2
11 = Current power state is D3
†
These bits are reset on the rising edge of PCI bus reset (PRST).
7.20 Power Management Extension Registers
The power management extension register provides extended power-management features not applicable
to the OHCI controller; thus, it is read-only and returns 0000h when read. See Table 7−16 for a complete
description of the register contents.
PCI register offset: 4Ah
Register type: Read-only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 7−16. Power Management Extension Registers Description
BIT FIELD NAME TYPE DESCRIPTION
15−0 RSVD R Reserved. Bits 15−0 return 0000h when read.
Not Recommended for New Designs