Datasheet

1394 OHCI—PCI Configuration Space
116
March 5 2007 − June 2011SCPS154C
7.5 Class Code and Revision ID Register
The class code and revision ID register categorizes the OHCI controller as a serial bus controller (0Ch),
controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision
is indicated in the least significant byte. See Table 7−4 for a complete description of the register contents.
PCI register offset: 08h
Register type: Read-only
Default value: 0C00 1001h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
Table 7−4. Class Code and Revision ID Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−24 BASECLASS R Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus
controller.
23−16 SUBCLASS R Subclass. This field returns 00h when read, which specifically classifies the function as controlling an
IEEE 1394 serial bus.
15−8 PGMIF R Programming interface. This field returns 10h when read, which indicates that the programming model
is compliant with the 1394 Open Host Controller Interface Specification.
7−0 CHIPREV R Silicon revision. This field returns 01h when read, which indicates the silicon revision of the OHCI
controller.
7.6 Latency Timer and Class Cache Line Size Register
The latency timer and class cache line size register is programmed by host BIOS to indicate system cache
line size and the latency timer associated with the OHCI controller. See Table 7−5 for a complete description
of the register contents.
PCI register offset: 0Ch
Register type: Read/Write
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 7−5. Latency Timer and Class Cache Line Size Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 LATENCY_TIMER RW PCI latency timer. The value in this register specifies the latency timer for the OHCI controller, in units
of PCI clock cycles. When the OHCI controller is a PCI bus initiator and asserts FRAME
, the latency
timer begins counting from 0. If the latency timer expires before the OHCI controller transaction has
terminated, then the OHCI controller terminates the transaction when its GNT
is deasserted. The
default value for this field is 00h.
7−0 CACHELINE_SZ RW Cache line size. This value is used by the OHCI controller during memory write and invalidate,
memory-read line, and memory-read multiple transactions. The default value for this field is 00h.
Not Recommended for New Designs