Datasheet

1394 OHCI—PCI Configuration Space
114
March 5 2007 − June 2011SCPS154C
7.2 Device ID Register
The device ID register contains a value assigned to the 1394 OHCI function by Texas Instruments. The device
identification for the 1394 OHCI function is 8235h.
PCI register offset: 02h
Register type: Read-only
Default value: 8235h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 1 0 0 0 0 0 1 0 0 0 1 1 0 1 0 1
7.3 Command Register
The command register provides control over the OHCI controller interface to the PCI bus. All bit functions
adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See
Table 7−2 for a complete description of the register contents.
PCI register offset: 04h
Register type: Read/Write, Read-only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 7−2. Command Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−11 RSVD R Reserved. Bits 15−11 return 0 0000b when read.
10 INT_DISABLE R Interrupt disable. When bit 10 is set to 1b, the OHCI controller is disabled from asserting an interrupt.
When cleared, the OHCI controller is able to send interrupts normally. This default value for this bit is
0b.
9 FBB_ENB R Fast back-to-back enable. The OHCI controller does not generate fast back-to-back transactions;
therefore, bit 9 returns 0b when read.
8 SERR_ENB RW PCI_SERR enable. When bit 8 is set to 1b, the OHCI controller PCI_SERR driver is enabled.
PCI_SERR
can be asserted after detecting an address parity error on the PCI bus. The default value
for this bit is 0b.
7 STEP_ENB R Address/data stepping control. The OHCI controller does not support address/data stepping;
therefore, bit 7 is hardwired to 0b.
6 PERR_ENB RW Parity error enable. When bit 6 is set to 1b, the OHCI controller is enabled to drive PCI_PERR response
to parity errors through the PCI_PERR
signal. The default value for this bit is 0b.
5 VGA_ENB R VGA palette snoop enable. The OHCI controller does not feature VGA palette snooping; therefore, bit
5 returns 0b when read.
4 MWI_ENB RW Memory write and invalidate enable. When bit 4 is set to 1b, the OHCI controller is enabled to generate
MWI PCI bus commands. If this bit is cleared, then the OHCI controller generates memory write
commands instead. The default value for this bit is 0b.
3 SPECIAL R Special cycle enable. The OHCI controller function does not respond to special cycle transactions;
therefore, bit 3 returns 0b when read.
2 MASTER_ENB RW Bus master enable. When bit 2 is set to 1b, the OHCI controller is enabled to initiate cycles on the PCI
bus. The default value for this bit is 0b.
1 MEMORY_ENB RW Memory response enable. Setting bit 1 to 1b enables the OHCI controller to respond to memory cycles
on the PCI bus. This bit must be set to access OHCI registers. The default value for this bit is 0b.
0 IO_ENB R I/O space enable. The OHCI controller does not implement any I/O-mapped functionality; therefore,
bit 0 returns 0b when read.
Not Recommended for New Designs