Datasheet

1394 OHCI—PCI Configuration Space
113
March 5 2007 − June 2011 SCPS154C
7 1394 OHCI—PCI Configuration Space
The 1394 OHCI core is integrated as a PCI device behind the PCI-Express to PCI Bridge. The configuration
header for the 1394 OHCI portion of the design is compliant with the PCI Specification as a standard header.
Table 7−1 illustrates the configuration header that includes both the predefined portion of the configuration
space and the user definable registers.
Since the 1394 OHCI configuration space is accessed over the bridge secondary PCI bus, PCI Express type
1 configuration read and write transactions are required when accessing these registers. The 1394 OHCI
configuration register map is accessed as device number 0 and function number 0. Of course, the bus number
is determined by the value that is loaded into the Secondary Bus Number field at offset 19h within the PCI
Express configuration register map.
All bits marked with a † are reset by a PCI Express reset (PERST
), a GRST, or the internally-generated
power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST
, GRST, or the
internally-generated power-on reset.
Table 7−1. 1394 OHCI Configuration Register Map
REGISTER NAME OFFSET
Device ID Vendor ID 00h
Status Command 04h
Class code Revision ID 08h
BIST Header type Latency timer Cache line size 0Ch
OHCI base address 10h
TI extension base address 14h
CIS base address 18h
Reserved 1Ch−27h
CIS pointer 28h
Subsystem ID† Subsystem vendor ID† 2Ch
Reserved 30h
Reserved PCI power management capabilities pointer 34h
Reserved 38h
Maximum latency† Minimum grant† Interrupt pin Interrupt line 3Ch
PCI OHCI control 40h
Power management capabilities Next item pointer Capability ID 44h
PM data (RSVD) PMCSR_BSE Power management control and status† 48h
Reserved 4Ch−EBh
PCI PHY control† ECh
Miscellaneous configuration† F0h
Link enhancement control† F4h
Subsystem access† F8h
TI proprietary FCh
†
One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
7.1 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the OHCI
controller. The vendor ID assigned to Texas Instruments is 104Ch.
PCI register offset: 00h
Register type: Read-only
Default value: 104Ch
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0
Not Recommended for New Designs