Datasheet

Memory-Mapped TI Proprietary Register Space
112
March 5 2007 − June 2011SCPS154C
6.23 TI Proprietary Register
This read/write TI proprietary register is located at offset 48h and controls TI proprietary functions. This
register must not be changed from the specified default state. This register is reset by a PCI Express reset
(PERST
), a GRST, or the internally-generated power-on reset.
Device control memory window register offset: 48h
Register type: Read-only, Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
6.24 TI Proprietary Register
This read/write TI proprietary register is located at offset 4Ah and controls TI proprietary functions. This
register must not be changed from the specified default state. This register is reset by a PCI Express reset
(PERST
), a GRST, or the internally-generated power-on reset.
Device control memory window register offset: 4Ah
Register type: Read/Write
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.25 TI Proprietary Register
This read/write TI proprietary register is located at offset 4Ch and controls TI proprietary functions. This
register must not be changed from the specified default state.
Device control memory window register offset: 4Ch
Register type: Read/Clear
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Not Recommended for New Designs