Datasheet

Memory-Mapped TI Proprietary Register Space
109
March 5 2007 − June 2011 SCPS154C
6.18 GPIO Data Register
This register reads the state of the input mode GPIO terminals and changes the state of the output mode GPIO
terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary
functions share GPIO4 (SCL) and GPIO5 (SDA). The default value at power up depends on the state of the
GPIO terminals as they default to general-purpose inputs. This register is an alias of the GPIO data register
in the classic PCI configuration space (offset B6h, see Section 4.60). See Table 6−9 for a complete description
of the register contents.
Device control memory window register offset: 42h
Register type: Read-only, Read/Write
Default value: 00XXh
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 x x x x x x x x
Table 6−9. GPIO Data Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:8 RSVD R Reserved
7† GPIO7_Data RW
GPIO 7 data. This bit reads the state of GPIO7 when in input mode or changes the state of
GPIO7 when in output mode.
6† GPIO6_Data RW
GPIO 6 data. This bit reads the state of GPIO6 when in input mode or changes the state of
GPIO6 when in output mode.
5† GPIO5_Data RW
GPIO 5 data. This bit reads the state of GPIO5 when in input mode or changes the state of
GPIO5 when in output mode.
4† GPIO4_Data RW
GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of
GPIO4 when in output mode.
3† GPIO3_Data RW
GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of
GPIO3 when in output mode.
2† GPIO2_Data RW
GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of
GPIO2 when in output mode.
1† GPIO1_Data RW
GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of
GPIO1 when in output mode.
0† GPIO0_Data RW
GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of
GPIO0 when in output mode.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
6.19 Serial-Bus Data Register
The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this
register prior to writing the serial-bus slave address register that initiates the bus cycle. When reading data
from the serial bus, this register contains the data read after bit 5 (REQBUSY) in the serial-bus control and
status register (offset 47h, see Section 6.22) is cleared. This register is an alias for the serial-bus data register
in the PCI header (offset B0h, see Section 4.55). This register is reset by a PCI Express reset (PERST
), a
GRST
, or the internally-generated power-on reset.
Device control memory window register offset: 44h
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Not Recommended for New Designs