Datasheet

Memory-Mapped TI Proprietary Register Space
103
March 5 2007 − June 2011 SCPS154C
6.3 Upstream Isochrony Capabilities Register
The upstream isochronous capabilities register provides software information regarding the capabilities
supported by this bridge. See Table 6−2 for a complete description of the register contents.
Device control memory window register offset: 02h
Register type: Read-only
Default value: 0004h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Table 6−2. Upstream Isochronous Capabilities Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:4 RSVD R Reserved. Returns 000h when read.
3:0 ISOC_WINDOW_COUNT R
Isochronous window count. This 4-bit field indicates the number of isochronous address
windows supported. The value 0100b indicates that 4 separate windows are supported
by the bridge.
6.4 Upstream Isochrony Control Register
The upstream isochrony control register allows software to control bridge isochronous behavior. See
Table 6−3 for a complete description of the register contents.
Device control memory window register offset: 04h
Register type: Read-only, Read/Write
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 6−3. Upstream Isochrony Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:3 RSVD R Reserved. Returns 0 0000 0000 0000b when read.
2 PORTARB_LEVEL_2_EN RW
Port arbitration level 2 enable. This bit is only valid if PORTARB_LEVEL_1_EN is set to
1b, because this enhances the behavior enabled through the assertion of that bit. If
PORTARB_LEVEL_1_EN is clear, then this bit is read-only and returns 0b when read.
0 = Arbiter behavior follows PORTARB_LEVEL_1_EN rules (default)
1 = Aggressive mode. The arbiter deliberately stops secondary bus masters in the
middle of their transaction to assure that isochrony is preserved.
1 PORTARB_LEVEL_1_EN RW
Port arbitration level 1 enable.
0 = Arbiter behavior is controlled only by the arbiter control registers within the classic
PCI configuration space (default)
1 = Values programmed within the port arbitration table for extended VCs impact the
arbiter’s decision to assert GNT
to any particular bus master. Programmed values
in the arbiter control registers within the classic PCI configuration space have no
effect when this bit is asserted.
0 ISOC_ENABLE RW
Isochronous enable. Global enable bit for the upstream isochronous capability of the
bridge.
0 = Mapping of upstream traffic to TCs other than TC0 prohibited (default)
1 = Mapping of upstream traffic to TCs other than TC0 permitted
Not Recommended for New Designs