Datasheet

PCI Express Extended Configuration Space
95
March 5 2007 − June 2011 SCPS154C
5.21 VC Resource Capability Register (VC0)
The VC resource capability register for VC0 provides information to software regarding the port and arbitration
schemes supported by the bridge. See Table 5−17 for a complete description of the register contents.
PCI Express extended register offset: 160h
Register type: Read-only
Default value: 0000 0001h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Table 5−17. VC Resource Capability Register (VC0) Description
BIT FIELD NAME ACCESS DESCRIPTION
31:24
PORT_ARB_TBL_
OFFSET
R
Port arbitration table offset. This read-only field returns the value 00h to indicate that no port
arbitration table is required for this VC.
23 RSVD R Reserved. Returns 0b when read.
22:16 MAX_TIME_SLOTS R
Maximum time slots. The read-only field returns the value 00h because there is no support for
time-based, WRR arbitration on this VC.
15 REJECT_SNOOP R
Reject snoop transactions. This bit only has meaningful context for root ports and therefore
returns 0b when read.
14 ADV_SWITCHING R
Advanced packet switching. This read-only bit returns 0b to indicate that the use of this VC is
not limited to AS traffic.
13:8 RSVD R Reserved. Returns 00 0000b when read.
7:0 PORT_ARB_CAP R
Port arbitration capability. This 8-bit encoded field indicates support for the various schemes
that are supported for port (secondary PCI device) arbitration. The field is encoded as follows:
Bit 0 = Hardware fixed arbitration (round-robin)
Bit 1 = WRR with 32 phases
Bit 2 = WRR with 64 phases
Bit 3 = WRR with 128 phases
Bit 4 = Time-based WRR with 128 phases
Bit 5 = WRR with 256 phases
Bit 6 = Reserved
Bit 7 = Reserved
The returned value of 01h indicates that only hardware-fixed, round-robin arbitration is
supported for this VC.
Not Recommended for New Designs