Datasheet

PCI Express Extended Configuration Space
93
March 5 2007 − June 2011 SCPS154C
5.18 Port VC Capability Register 2
The second port VC capability register provides information to software regarding the VC arbitration schemes
supported by the bridge. See Table 5−14 for a complete description of the register contents.
PCI Express extended register offset: 158h
Register type: Read-only
Default value: 0X00 000Xh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 x x 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x
Table 5−14. Port VC Capability Register 2 Description
BIT FIELD NAME ACCESS DESCRIPTION
31:24
VC_ARB_
TBL_OFFSET
RU
VC arbitration table offset. If bits 6:4 (LOW_PRIORITY_COUNT) in the port VC capability register 1
(offset 154h, see Section 5.17) are 000b, then this field returns 00h when read. Otherwise, this
read-only field returns the value 03h to indicate that the VC arbitration table begins 48 bytes from the
top of the VC capability structure. When this field equals 00h, the VC arbitration table is a scratch
pad and has no effect in the bridge.
23:8 RSVD R Reserved. Returns 0000h when read.
7:0
VC_ARB
_CAP
RU
VC arbitration capability. This 8-bit encoded field indicates support for the various schemes that are
supported for VC arbitration. The field is encoded as follows:
Bit 0 = Hardware fixed arbitration (round-robin)
Bit 1 = WRR with 32 phases
Bit 2 = WRR with 64 phases
Bit 3 = WRR with 128 phases
Bit 4 = Reserved
Bit 5 = Reserved
Bit 6 = Reserved
Bit 7 = Reserved
If bits 6:4 (LOW_PRIORITY_COUNT) in the port VC capability register 1 (offset 154h, see
Section 5.17) are 000b, then this field returns 00h when read. Otherwise, this field returns 03h to
indicate that hardware-fixed round-robin and WRR with 32 phases are both supported.
Not Recommended for New Designs