Datasheet

PCI Express Extended Configuration Space
91
March 5 2007 − June 2011 SCPS154C
5.14 Secondary Header Log Register
The secondary header log register stores the transaction address and command for the PCI bus cycle that
led to the most recently detected error condition. Offset 13Ch accesses register bits 31:0. Offset 140h
accesses register bits 63:32. Offset 144h accesses register bits 95:64. Offset 148h accesses register
bits 127:96. See Table 5−12 for a complete description of the register contents.
PCI Express extended register offset: 13Ch, 140h, 144h, and 148h
Register type: Read-only
Default value: 0000 0000h
BIT NUMBER 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 5−12. Secondary Header Log Register Description
BIT FIELD NAME ACCESS DESCRIPTION
127:64† ADDRESS RU
Transaction address. The 64-bit value transferred on AD[31:0] during the first and second
address phases. The first address phase is logged to 95:64 and the second address phase
is logged to 127:96. In the case of a 32-bit address, bits 127:96 are set to 0.
63:44 RSVD R Reserved. Returns 0 0000h when read.
43:40† UPPER_CMD RU
Transaction command upper. Contains the status of the C/BE terminals during the second
address phase of the PCI transaction that generated the error if using a dual-address cycle.
39:36† LOWER_CMD RU
Transaction command lower. Contains the status of the C/BE terminals during the first
address phase of the PCI transaction that generated the error.
35:0 TRANS_ATTRIBUTE R
Transaction attribute. Because the bridge does not support the PCI-X attribute transaction
phase, these bits have no function, and return 0 0000 0000h when read.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
5.15 Virtual Channel Capability ID Register
This read-only register identifies the linked list item as the register for PCI Express VC capabilities. The register
returns 0002h when read.
PCI Express extended register offset: 150h
Register type: Read-only
Default value: 0002h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Not Recommended for New Designs