Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsPCB design board

XIO2200A PCI Express to PCI Bus

Translation Bridge with 1394a OHCI

and Two-Port PHY

Data Manual

Literature Number: SCPS154C

March 5 2007 − June 2011

Printed on Recycled Paper

Not Recommended for New Designs

Summary of content (202 pages)

PAGE 1
Not Recommended for New Designs XIO2200A PCI Express to PCI Bus Translation Bridge with 1394a OHCI and Two-Port PHY Data Manual Literature Number: SCPS154C March 5 2007 − June 2011 Printed on Recycled Paper
PAGE 2
Not Recommended for New Designs Section 1 2 3 Contents Page XIO2200 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
Not Recommended for New Designs Contents Section 4 iv Page Classic PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.
PAGE 4
Not Recommended for New Designs Section 5 Page 4.48 PCI Express Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.49 Device Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.50 Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.
PAGE 5
Not Recommended for New Designs Contents Section 6 7 vi Page 5.21 VC Resource Capability Register (VC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.22 VC Resource Control Register (VC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.23 VC Resource Status Register (VC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.
PAGE 6
Not Recommended for New Designs Section 8 Page 7.14 Interrupt Line and Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.15 MIN_GNT and MAX_LAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.16 OHCI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.
PAGE 7
Not Recommended for New Designs Contents Section 9 10 11 12 13 viii Page 8.36 Asynchronous Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.37 Physical Request Filter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.38 Physical Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.
PAGE 8
Not Recommended for New Designs List of Tables Table 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 2−9 2−10 2−11 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 3−11 3−12 3−13 3−14 4−1 4−2 4−3 4−4 4−5 4−6 4−7 4−8 4−9 4−10 4−11 4−12 4−13 4−14 4−15 4−16 4−17 4−18 4−19 4−20 4−21 4−22 Page XIO2200 GGW/ZGW Terminals Sorted Alphanumerically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XIO2200 ZHH Terminals Sorted Alphanumerically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 9
Not Recommended for New Designs Tables Table 4−23 4−24 4−25 4−26 4−27 4−28 4−29 4−30 4−31 4−32 4−33 4−34 4−35 4−36 4−37 4−38 4−39 4−40 4−41 4−42 5−1 5−2 5−3 5−4 5−5 5−6 5−7 5−8 5−9 5−10 5−11 5−12 5−13 5−14 5−15 5−16 5−17 5−18 5−19 5−20 5−21 5−22 5−23 5−24 5−25 5−26 6−1 6−2 x Page MSI Message Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 10
Not Recommended for New Designs Table 6−3 6−4 6−5 6−6 6−7 6−8 6−9 6−10 6−11 7−1 7−2 7−3 7−4 7−5 7−6 7−7 7−8 7−9 7−10 7−11 7−12 7−13 7−14 7−15 7−16 7−17 7−18 7−19 7−20 8−1 8−2 8−3 8−4 8−5 8−6 8−7 8−8 8−9 8−10 8−11 8−12 8−13 8−14 8−15 8−16 8−17 8−18 8−19 Page Upstream Isochrony Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Upstream Isochronous Window 0 Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 11
Not Recommended for New Designs Tables Table 8−20 8−21 8−22 8−23 8−24 8−25 8−26 8−27 8−28 8−29 8−30 8−31 8−32 8−33 8−34 8−35 9−1 9−2 9−3 9−4 10−1 10−2 10−3 10−4 10−5 10−6 10−7 10−8 10−9 xii Page Initial Channels Available High Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initial Channels Available Low Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fairness Control Register Description . . . . . . . . .
PAGE 12
Not Recommended for New Designs List of Figures Figure 2−1 2−2 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 3−11 3−12 11−1 Page XIO2200 GGW/ZGW MicroStar BGAt Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . XIO2200 ZHH MicroStar BGAt Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XIO2200 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 13
Not Recommended for New Designs Figures (This page has been left blank intentionally.
PAGE 14
Not Recommended for New Designs Features 1 XIO2200A Features D Full x1 PCI Express Throughput D Fully Compliant with PCI Express to D D D D D D D D PCI/PCI-X Bridge Specification, Revision 1.0 Fully Compliant with PCI Express Base Specification, Revision 1.0a Fully Compliant with PCI Local Bus Specification, Revision 2.
PAGE 15
Not Recommended for New Designs Introduction 2 Introduction The Texas Instruments XIO2200A is a single-function PCI Express to PCI local bus translation bridge where the PCI bus interface is internally connected to a 1394a-2000 open host controller link-layer controller with a two-port 1394a PHY. When the XIO2200A is properly configured, this solution provides full PCI Express and 1394a functionality and performance. 2.
PAGE 16
Not Recommended for New Designs Introduction 2.2 Related Documents • • • • • • • • • • • 2.3 Trademarks • • • 2.4 PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 PCI Express Base Specification, Revision 1.0a PCI Express Card Electromechanical Specification, Revision 1.0a PCI Local Bus Specification, Revision 2.3 PCI-to-PCI Bridge Architecture Specification, Revision 1.2 PCI Bus Power Management Interface Specification, Revision 1.1 or 1.
PAGE 17
Not Recommended for New Designs Introduction 2.5 Document History REVISION DATE REVISION NUMBER 08/2005 − Initial release 01/2007 − Add ZHH package information 2.6 2.7 REVISION COMMENTS Ordering Information ORDERING NUMBER NAME VOLTAGE PACKAGE XIO2200A PCI-Express to PCI Translation Bridge with 1394a OHCI and Two-Port PHY 3.3-V and 1.5-V power terminals 176-terminal GGW MicroStar BGA XIO2200A PCI-Express to PCI Translation Bridge with 1394a OHCI and Two-Port PHY 3.3-V and 1.
PAGE 18
Not Recommended for New Designs Introduction 1 U 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RSVD RSVD RSVD GPIO1 GPIO3 GPIO6 GPIO7 CNA PC0 TPB0N TPA0N TPBIAS 0 TPB1N TPA1N TPBIAS 1 RSVD RSVD GPIO0 GPIO2 GPIO5 // SDA RSVD PC1 CPS TPB0P TPA0P VDDA_ 33 TPB1P TPA1P VSS VDD_33 VSS GPIO4 // SCL RSVD PC2 VSSA VSSA VSSA VSSA VDDA_ 33 VDD_15 VSS VDD_33 VDDA_ 33 VDDA_ 33 T RSVD R RSVD RSVD P RSVD RSVD RSVD N RSVD RSVD M RSVD L 17 R0_ 1394 R1_ 1394
PAGE 19
Not Recommended for New Designs Introduction Table 2−1.
PAGE 20
Not Recommended for New Designs Introduction Table 2−1.
PAGE 21
Not Recommended for New Designs Introduction 01 02 03 04 05 06 07 08 09 10 11 12 13 14 P RSVD RSVD RSVD GPIO0 GPIO4 //SCL RSVD PC2 TPB0P TPA0P TPB1P TPA1P TPBIAS1 VSSA R0_1394 P N RSVD RSVD RSVD GPIO2 GPIO5 //SDA CNA PC0 TPBoN TPA0N TPB1N TPA1N VDD_15 VSSA R1_1394 N M RSVD RSVD RSVD GPIO3 GPIO6 RSVD PC1 VSSA VDDA_ 33 VDDA_ 33 VDDA_ 33 RSVD XO XI M L RSVD RSVD RSVD RSVD VDD_15 GPIO7 CPS VDDA_ 33 VSSA TPBIAS0 VSSA RSVD GRST RSVD L K
PAGE 22
Not Recommended for New Designs Introduction Table 2−2.
PAGE 23
Not Recommended for New Designs Introduction Table 2−2.
PAGE 24
Not Recommended for New Designs Introduction Table 2−3.
PAGE 25
Not Recommended for New Designs Introduction Table 2−3.
PAGE 26
Not Recommended for New Designs Introduction 2.8 Terminal Descriptions Table 2−4 through Table 2−11 give a description of the terminals. These terminals are grouped in tables by functionality. Each table includes the terminal name, terminal number, I/O type, and terminal description.
PAGE 27
Not Recommended for New Designs Introduction Table 2−7. PCI Express Terminals SIGNAL PERST GGW/ ZGW BALL # J17 ZHH BALL # H12 I/O TYPE CELL TYPE CLAMP RAIL I LV CMOS VDD_33_ COMBIO EXTERNAL PARTS − DESCRIPTION PCI Express reset input. The PERST signal identifies when the system power is stable and generates an internal power-on reset. Note: The PERST input buffer has hysteresis. External reference resistor + and − terminals for setting TX driver current.
PAGE 28
Not Recommended for New Designs Introduction Table 2−9. 1394 Terminals SIGNAL CNA GGW/ ZGW BALL # ZHH BALL # I/O TYPE CELL TYPE EXTERNAL PARTS U09 N06 I/O LV CMOS − I Feed through External resistor per 1394a specification Cable power status input. This terminal is normally connected to cable power through a 400-kΩ resistor. This circuit drives an internal comparator that detects the presence of cable power.
PAGE 29
Not Recommended for New Designs Introduction RSVD B08, B11, B12, B13, C09, C10, E01, F01, F02, F03, G01, G02, G03, R01, R02, T01, T03, U02 A08, A10, A11, A12, B07, C09, D01, D03, E01, E02, E03, E04, F01, M01, M02, M03, N01, N02 I Must be connected to VDD_33. RSVD A15, B15, D16, D17, P03, T04 B12, B13, D13, D14, L03, N03 I Must be connected to VSS. RSVD M15 L12 I If the VAUX supply is present, connect this terminal to VDD_33_AUX.
PAGE 30
Not Recommended for New Designs Introduction Table 2−11. Miscellaneous Terminals SIGNAL GPIO0 GGW/ ZGW BALL # ZHH BALL # T05 P03 I/O TYPE CELL TYPE I/O LV CMOS CLAMP RAIL VDD_33 EXTERNAL PARTS − DESCRIPTION General-purpose I/O 0. This terminal functions as a GPIO controlled by bit 0 (GPIO0_DIR) in the GPIO control register (see Section 4.59). Note: This terminal has an internal active pullup resistor. GPIO1 U05 P04 I/O LV CMOS VDD_33 − General-purpose I/O 1.
PAGE 31
Not Recommended for New Designs Feature/Protocol Descriptions 3 Feature/Protocol Descriptions This chapter provides a high-level overview of all significant device features. Figure 3−1 shows a simplified block diagram of the basic architecture of the PCI-Express to PCI Bridge with 1394a OHCI and two-port PHY. The top of the diagram is the PCI Express interface and the 1394a OHCI with two-port PHY is located at the bottom of the diagram.
PAGE 32
Not Recommended for New Designs Feature/Protocol Descriptions 3.1.1 Power-Up Sequence 1. Assert PERST to the device. 2. Apply 1.5-V and 3.3-V voltages. 3. Apply a stable PCI Express reference clock. 4. To meet PCI Express specification requirements, PERST cannot be deasserted until the following two delay requirements are satisfied: − Wait a minimum of 100 μs after applying a stable PCI Express reference clock.
PAGE 33
Not Recommended for New Designs Feature/Protocol Descriptions 3.1.2 Power-Down Sequence 1. Assert PERST to the device. 2. Remove the reference clock. 3. Remove 3.3-V and 1.5-V voltages. Please see the power-down sequencing diagram in Figure 3−3. If the VDD_33_AUX terminal is to remain powered after a system shutdown, then the bridge power-down sequence is exactly the same as shown in Figure 3−3. VDD_15 VDDA_15 VDD_33 VDDA_33 REFCLK PERST Figure 3−3. Power-Down Sequence 3.
PAGE 34
Not Recommended for New Designs Feature/Protocol Descriptions Table 3−1. Bridge Reset Options RESET OPTION Bridge internally-generated power-on reset Global reset input GRST (N17) XIO2200A FEATURE RESET RESPONSE During a power-on cycle, the bridge asserts an internal reset and monitors the VDD_15_COMB (M17) terminal. When this terminal reaches 90% of the nominal input voltage specification, power is considered stable.
PAGE 35
Not Recommended for New Designs Feature/Protocol Descriptions If the REFCLK_SEL (A16) input is connected to VSS, then a differential, 100-MHz common clock reference is expected by the bridge. If the A16 terminal is connected to VDD_33, then a single-ended, 125-MHz clock reference is expected by the bridge. When the single-ended, 125-MHz clock reference option is enabled, the single-ended clock signal is connected to the REFCLK+ (C17) terminal.
PAGE 36
Not Recommended for New Designs Feature/Protocol Descriptions Table 3−3.
PAGE 37
Not Recommended for New Designs Feature/Protocol Descriptions 5. When programming the upstream isochronous window base and limit registers, the 32-bit base/limit address must be DWORD aligned and the limit address must be greater than the base address. The following sections describe in detail the standard and advanced bridge features for QoS and isochronous applications. 3.4.1 PCI Port Arbitration The internal PCI port arbitration logic supports the internal 1394a OHCI and the bridge PCI bus devices.
PAGE 38
Not Recommended for New Designs Feature/Protocol Descriptions Table 3−6 identifies and describes the registers associated with 128-phase, WWR time-based arbitration mode. Table 3−6. 128-Phase, WRR Time-Based Arbiter Registers REGISTER OFFSET REGISTER NAME DESCRIPTION PCI Express VC extended configuration registers 1C0h to 1FCh Port arbitration table (see Section 5.28) 16-doubleword sized configuration registers that are the registered version of the 128-phase, WRR port arbitration table.
PAGE 39
Not Recommended for New Designs Feature/Protocol Descriptions 3.4.3 PCI Express Extended VC With VC Arbitration When a second VC is enabled, the bridge has three arbitration options that determine which VC is granted access to the upstream PCI Express link. These three arbitration modes include strict priority, hardware-fixed round-robin, and 32-phase WRR. The default mode is strict priority. For all three arbitration modes, if the second VC is disabled, then VC0 is always granted.
PAGE 40
Not Recommended for New Designs Feature/Protocol Descriptions Table 3−9. 32-Phase, WRR Arbiter Registers PCI OFFSET REGISTER NAME DESCRIPTION Classic PCI configuration register D4h General control (see Section 4.65) Bit 25 (STRICT_PRIORITY_EN) equal to 0b enables either hardware-fixed, round-robin or 32-phase, WRR arbitration mode. PCI Express VC extended configuration register 15Ch Port VC control (see Section 5.
PAGE 41
Not Recommended for New Designs Feature/Protocol Descriptions 3.5 PCI Interrupt Conversion to PCI Express Messages The bridge converts interrupts from the PCI bus sideband interrupt signals to PCI Express interrupt messages. Since the 1394a OHCI only generates INTA interrupts, only PCI Express INTA messages are generated by the bridge. PCI Express Assert_INTA messages are generated when the 1394a OHCI signals an INTA interrupt.
PAGE 42
Not Recommended for New Designs Feature/Protocol Descriptions The bridge implements a two-terminal serial interface with one clock signal (SCL) and one data signal (SDA). The SCL signal is a unidirectional output from the bridge and the SDA signal is bidirectional. Both are open-drain signals and require pullup resistors. The bridge is a bus master device and drives SCL at approximately 60 kHz during data transfers and places SCL in a high-impedance state (0 frequency) during bus idle states.
PAGE 43
Not Recommended for New Designs Feature/Protocol Descriptions SCL From Master 1 2 3 7 8 9 SDA Output By Transmitter SDA Output By Receiver Figure 3−9. Serial-Bus Protocol Acknowledge The bridge performs three basic serial-bus operations: single byte reads, single byte writes, and multibyte reads. The single byte operations occur under software control. The multibyte read operations are performed by the serial EEPROM initialization circuitry immediately after a PCI Express reset. See Section 3.6.
PAGE 44
Not Recommended for New Designs Feature/Protocol Descriptions Slave Address S Word Address b6 b5 b4 b3 b2 b1 b0 Start 0 A Slave Address b7 b6 b5 b4 b3 b2 b1 b0 A S b6 b5 b4 b3 b2 b1 b0 Restart R/W 1 A R/W Data Byte b7 b6 b5 b4 b3 b2 b1 b0 M P Stop A = Slave Acknowledgement M = Master Acknowledgement S/P = Start/Stop Condition Figure 3−11. Serial-Bus Protocol—Byte Read Figure 3−12 illustrates the serial interface protocol during a multi-byte serial EEPROM download.
PAGE 45
Not Recommended for New Designs Feature/Protocol Descriptions Table 3−10.
PAGE 46
Not Recommended for New Designs Feature/Protocol Descriptions Table 3−10.
PAGE 47
Not Recommended for New Designs Feature/Protocol Descriptions Table 3−11. Registers Used To Program Serial-Bus Devices PCI OFFSET REGISTER NAME DESCRIPTION B0h Serial-bus data (see Section 4.55) Contains the data byte to send on write commands or the received data byte on read commands. B1h Serial-bus word address (see Section 4.56) The content of this register is sent as the word address on byte writes or reads. This register is not used in the quick command protocol.
PAGE 48
Not Recommended for New Designs Feature/Protocol Descriptions 3.9 General-Purpose I/O Interface Up to eight general-purpose input/output (GPIO) terminals are provided for system customization. These GPIO terminals are 3.3-V tolerant. The exact number of GPIO terminals varies based on implementing the clock run, power override, and serial EEPROM interface features. These features share four of the eight GPIO terminals.
PAGE 49
Not Recommended for New Designs Feature/Protocol Descriptions Finally, the bridge generates the PM_Active_State_Nak Message if a PM_Active_State_Request_L1 DLLP is received on the PCI Express interface and the link cannot be transitioned to L1. 3.12 1394a OHCI Controller Functionality 3.12.1 1394a OHCI Power Management The 1394a OHCI controller complies with the PCI Bus Power Management Interface Specification.
PAGE 50
Not Recommended for New Designs Feature/Protocol Descriptions Table 3−14. 1394a OHCI Memory Command Options 3.12.
PAGE 51
Not Recommended for New Designs Classic PCI Configuration Space 4 Classic PCI Configuration Space The programming model of the XIO2200A PCI-Express to PCI bridge is compliant to the classic PCI-to-PCI bridge programming model. The PCI configuration map uses the type 1 PCI bridge header. All bits marked with a k are sticky bits and are reset by a global reset (GRST) or the internally-generated power-on reset.
PAGE 52
Not Recommended for New Designs Classic PCI Configuration Space Table 4−1.
PAGE 53
Not Recommended for New Designs Classic PCI Configuration Space 4.3 Command Register The command register controls how the bridge behaves on the PCI Express interface. See Table 4−2 for a complete description of the register contents. PCI register offset: Register type: Default value: 04h Read-only, Read/Write 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4−2.
PAGE 54
Not Recommended for New Designs Classic PCI Configuration Space 4.4 Status Register The status register provides information about the PCI Express interface to the system. See Table 4−3 for a complete description of the register contents. PCI register offset: Register type: Default value: 06h Read-only, Read/Clear 0010h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Table 4−3.
PAGE 55
Not Recommended for New Designs Classic PCI Configuration Space 4.5 Class Code and Revision ID Register This read-only register categorizes the base class, subclass, and programming interface of the bridge. The base class is 06h, identifying the device as a bridge. The subclass is 04h, identifying the function as a PCI-to-PCI bridge, and the programming interface is 00h. Furthermore, the TI device revision is indicated in the lower byte (03h).
PAGE 56
Not Recommended for New Designs Classic PCI Configuration Space 4.9 BIST Register Since the bridge does not support a built-in self test (BIST), this read-only register returns the value of 00h when read. PCI register offset: Register type: Default value: 0Fh Read-only 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 4.10 Device Control Base Address Register This register programs the memory base address that accesses the device control registers.
PAGE 57
Not Recommended for New Designs Classic PCI Configuration Space 4.12 Secondary Bus Number Register This read/write register specifies the bus number of the PCI bus segment that the PCI interface is connected to. The bridge uses this register to determine how to respond to a type 1 configuration transaction. PCI register offset: Register type: Default value: 19h Read/Write 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 4.
PAGE 58
Not Recommended for New Designs Classic PCI Configuration Space 4.16 I/O Limit Register This read/write register specifies the upper limit of the I/O addresses that the bridge forwards downstream. See Table 4−7 for a complete description of the register contents. PCI register offset: Register type: Default value: 1Dh Read-only, Read/Write 01h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 1 Table 4−7.
PAGE 59
Not Recommended for New Designs Classic PCI Configuration Space 4.17 Secondary Status Register The secondary status register provides information about the PCI bus interface. See Table 4−8 for a complete description of the register contents. PCI register offset: Register type: Default value: 1Eh Read-only, Read/Clear 02X0h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 1 0 1 0 x 0 0 0 0 0 Table 4−8.
PAGE 60
Not Recommended for New Designs Classic PCI Configuration Space 4.18 Memory Base Register This read/write register specifies the lower limit of the memory addresses that the bridge forwards downstream. See Table 4−9 for a complete description of the register contents. PCI register offset: Register type: Default value: 20h Read-only, Read/Write 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4−9.
PAGE 61
Not Recommended for New Designs Classic PCI Configuration Space 4.21 Prefetchable Memory Limit Register This read/write register specifies the upper limit of the prefetchable memory addresses that the bridge forwards downstream. See Table 4−12 for a complete description of the register contents.
PAGE 62
Not Recommended for New Designs Classic PCI Configuration Space 4.24 I/O Base Upper 16 Bits Register This read/write register specifies the upper 16 bits of the I/O base register. See Table 4−15 for a complete description of the register contents. PCI register offset: Register type: Default value: 30h Read/Write 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4−15.
PAGE 63
Not Recommended for New Designs Classic PCI Configuration Space 4.27 Interrupt Line Register This read/write register is programmed by the system and indicates to the software which interrupt line the bridge has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet been assigned to the function. Since the bridge does not generate interrupts internally, this register is a scratch pad register.
PAGE 64
Not Recommended for New Designs Classic PCI Configuration Space Table 4−17. Bridge Control Register Description (Continued) BIT FIELD NAME ACCESS 9 SEC_DT RW DESCRIPTION Selects the number of PCI clocks that the bridge waits for the 1394a OHCI master on the secondary interface to repeat a delayed transaction request. The counter starts once the delayed completion (the completion of the delayed transaction on the primary interface) has reached the head of the downstream queue of the bridge (i.e.
PAGE 65
Not Recommended for New Designs Classic PCI Configuration Space Table 4−17. Bridge Control Register Description (Continued) BIT FIELD NAME ACCESS DESCRIPTION 2 ISA RW ISA enable. This bit modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O base and I/O limit registers and are in the first 64 KB of PCI I/O address space (0000 0000h to 0000 FFFFh).
PAGE 66
Not Recommended for New Designs Classic PCI Configuration Space 4.32 Power Management Capabilities Register This read-only register indicates the capabilities of the bridge related to PCI power management. See Table 4−18 for a complete description of the register contents. PCI register offset: Register type: Default value: 52h Read-only 0602h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 Table 4−18.
PAGE 67
Not Recommended for New Designs Classic PCI Configuration Space 4.33 Power Management Control/Status Register This register determines and changes the current power state of the bridge. No internal reset is generated when transitioning from the D3hot state to the D0 state. See Table 4−19 for a complete description of the register contents.
PAGE 68
Not Recommended for New Designs Classic PCI Configuration Space 4.35 Power Management Data Register The read-only register is not applicable to the bridge and returns 00h when read. PCI register offset: Register type: Default value: 57h Read-only 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 4.36 MSI Capability ID Register This read-only register identifies the linked list item as the register for message signaled interrupts capabilities. The register returns 05h when read.
PAGE 69
Not Recommended for New Designs Classic PCI Configuration Space 4.38 MSI Message Control Register This register controls the sending of MSI messages. See Table 4−21 for a complete description of the register contents. PCI register offset: Register type: Default value: 62h Read-only, Read/Write 0088h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 Table 4−21.
PAGE 70
Not Recommended for New Designs Classic PCI Configuration Space 4.40 MSI Message Upper Address Register This register contains the upper 32 bits of the address that a MSI message writes to when a serial IRQ is detected. If this register contains 0000 0000h, then 32-bit addressing is used; otherwise, 64-bit addressing is used.
PAGE 71
Not Recommended for New Designs Classic PCI Configuration Space 4.43 Next Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This register reads 90h pointing to the PCI Express capabilities registers. PCI register offset: Register type: Default value: 81h Read-only 90h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 0 0 1 0 0 0 0 4.
PAGE 72
Not Recommended for New Designs Classic PCI Configuration Space 4.47 Next Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This register reads 00h indicating no additional capabilities are supported. PCI register offset: Register type: Default value: 91h Read-only 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 4.
PAGE 73
Not Recommended for New Designs Classic PCI Configuration Space 4.49 Device Capabilities Register The device capabilities register indicates the device specific capabilities of the bridge. See Table 4−25 for a complete description of the register contents.
PAGE 74
Not Recommended for New Designs Classic PCI Configuration Space 4.50 Device Control Register The device control register controls PCI Express device specific parameters. See Table 4−26 for a complete description of the register contents. PCI register offset: Register type: Default value: 98h Read-only, Read/Write 2800h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Table 4−26.
PAGE 75
Not Recommended for New Designs Classic PCI Configuration Space Table 4−26. Device Control Register Description (Continued) BIT 3 2 1 0 FIELD NAME URRE FERE NFERE CERE ACCESS DESCRIPTION Unsupported request reporting enable. If this bit is set, then the bridge sends an ERR_NONFATAL message to the root complex when an unsupported request is received.
PAGE 76
Not Recommended for New Designs Classic PCI Configuration Space 4.52 Link Capabilities Register The link capabilities register indicates the link specific capabilities of the bridge. See Table 4−28 for a complete description of the register contents.
PAGE 77
Not Recommended for New Designs Classic PCI Configuration Space 4.53 Link Control Register The link control register controls link specific behavior. See Table 4−29 for a complete description of the register contents. PCI register offset: Register type: Default value: A0h Read-only, Read/Write 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4−29.
PAGE 78
Not Recommended for New Designs Classic PCI Configuration Space 4.54 Link Status Register The link status register indicates the current state of the PCI Express link. See Table 4−30 for a complete description of the register contents. PCI register offset: Register type: Default value: A2h Read-only X011h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 x 0 0 0 0 0 0 0 1 0 0 0 1 Table 4−30.
PAGE 79
Not Recommended for New Designs Classic PCI Configuration Space 4.57 Serial-Bus Slave Address Register The serial-bus slave address register indicates the slave address of the device being targeted by the serial-bus cycle. This register also indicates if the cycle is a read or a write cycle. Writing to this register initiates the cycle on the serial interface. See Table 4−31 for a complete description of the register contents.
PAGE 80
Not Recommended for New Designs Classic PCI Configuration Space 4.58 Serial-Bus Control and Status Register The serial-bus control and status register controls the behavior of the serial-bus interface. This register also provides status information about the state of the serial bus. See Table 4−32 for a complete description of the register contents.
PAGE 81
Not Recommended for New Designs Classic PCI Configuration Space 4.59 GPIO Control Register This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior of GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO4 (SCL) and GPIO5 (SDA). See Table 4−33 for a complete description of the register contents.
PAGE 82
Not Recommended for New Designs Classic PCI Configuration Space 4.60 GPIO Data Register This register reads the state of the input mode GPIO terminals and changes the state of the output mode GPIO terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary functions share GPIO4 (SCL) and GPIO5 (SDA). The default value at power up depends on the state of the GPIO terminals as they default to general-purpose inputs.
PAGE 83
Not Recommended for New Designs Classic PCI Configuration Space 4.61 Control and Diagnostic Register 0 The contents of this register are used for monitoring status and controlling behavior of the bridge. See Table 4−35 for a complete description of the register contents. It is recommended that all values within this register be left at the default value. Improperly programming fields in this register may cause interoperability or other problems.
PAGE 84
Not Recommended for New Designs Classic PCI Configuration Space 4.62 Control and Diagnostic Register 1 The contents of this register are used for monitoring status and controlling behavior of the bridge. See Table 4−36 for a complete description of the register contents. It is recommended that all values within this register be left at the default value. Improperly programming fields in this register may cause interoperability or other problems.
PAGE 85
Not Recommended for New Designs Classic PCI Configuration Space 4.63 Control and Diagnostic Register 2 The contents of this register are used for monitoring status and controlling behavior of the bridge. See Table 4−37 for a complete description of the register contents. It is recommended that all values within this register be left at the default value. Improperly programming fields in this register may cause interoperability or other problems.
PAGE 86
Not Recommended for New Designs Classic PCI Configuration Space 4.65 General Control Register This read/write register controls various functions of the bridge. See Table 4−39 for a complete description of the register contents.
PAGE 87
Not Recommended for New Designs Classic PCI Configuration Space Table 4−39. General Control Register Description (Continued) BIT FIELD NAME 19† READ_ PREFETCH_ DIS ACCESS RW DESCRIPTION Read prefetch disable. This bit controls the prefetch functionality on PCI memory read transactions. 0 = Prefetch to the next cache line boundary on a burst read (default) 1 = Fetch only a single DWORD on a burst read L0s maximum exit latency.
PAGE 88
Not Recommended for New Designs Classic PCI Configuration Space 4.66 TI Proprietary Register This read/write TI proprietary register is located at offset D8h and controls TI proprietary functions. This register must not be changed from the specified default state. This register is reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
PAGE 89
Not Recommended for New Designs Classic PCI Configuration Space 4.69 Arbiter Control Register The arbiter control register controls the bridge internal arbiter. The arbitration scheme used is a two-tier rotational arbitration. The bridge is the only secondary bus master that defaults to the higher priority arbitration tier. See Table 4−40 for a complete description of the register contents.
PAGE 90
Not Recommended for New Designs Classic PCI Configuration Space 4.70 Arbiter Request Mask Register The arbiter request mask register enables and disables support for requests from specific masters on the secondary bus. The arbiter request mask register also controls if a request input is automatically masked on an arbiter time-out. See Table 4−41 for a complete description of the register contents.
PAGE 91
Not Recommended for New Designs Classic PCI Configuration Space 4.72 TI Proprietary Register This read/write TI proprietary register is located at offset E0h and controls TI proprietary functions. This register must not be changed from the specified default state. This register is reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
PAGE 92
Not Recommended for New Designs PCI Express Extended Configuration Space 5 PCI Express Extended Configuration Space The programming model of the PCI Express extended configuration space is compliant to the PCI Express Base Specification and the PCI Express to PCI/PCI-X Bridge Specification programming models. The PCI Express extended configuration map uses the PCI Express advanced error reporting capability and PCI Express virtual channel (VC) capability headers.
PAGE 93
Not Recommended for New Designs PCI Express Extended Configuration Space Table 5−1.
PAGE 94
Not Recommended for New Designs PCI Express Extended Configuration Space 5.3 Uncorrectable Error Status Register The uncorrectable error status register reports the status of individual errors as they occur on the primary PCI Express interface. Software may only clear these bits by writing a 1b to the desired location. See Table 5−2 for a complete description of the register contents.
PAGE 95
Not Recommended for New Designs PCI Express Extended Configuration Space 5.4 Uncorrectable Error Mask Register The uncorrectable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, PCI Express error messages are blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5−3 for a complete description of the register contents.
PAGE 96
Not Recommended for New Designs PCI Express Extended Configuration Space 5.5 Uncorrectable Error Severity Register The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is cleared, the corresponding error condition is identified as nonfatal. See Table 5−4 for a complete description of the register contents.
PAGE 97
Not Recommended for New Designs PCI Express Extended Configuration Space 5.6 Correctable Error Status Register The correctable error status register reports the status of individual errors as they occur. Software may only clear these bits by writing a 1b to the desired location. See Table 5−5 for a complete description of the register contents.
PAGE 98
Not Recommended for New Designs PCI Express Extended Configuration Space 5.7 Correctable Error Mask Register The correctable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, PCI Express error messages are blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5−6 for a complete description of the register contents.
PAGE 99
Not Recommended for New Designs PCI Express Extended Configuration Space 5.8 Advanced Error Capabilities and Control Register The advanced error capabilities and control register allows the system to monitor and control the advanced error reporting capabilities. See Table 5−7 for a complete description of the register contents.
PAGE 100
Not Recommended for New Designs PCI Express Extended Configuration Space 5.10 Secondary Uncorrectable Error Status Register The secondary uncorrectable error status register reports the status of individual PCI bus errors as they occur. Software may only clear these bits by writing a 1b to the desired location. See Table 5−8 for a complete description of the register contents.
PAGE 101
Not Recommended for New Designs PCI Express Extended Configuration Space 5.11 Secondary Uncorrectable Error Mask Register The secondary uncorrectable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, PCI Express error messages are blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5−9 for a complete description of the register contents.
PAGE 102
Not Recommended for New Designs PCI Express Extended Configuration Space 5.12 Secondary Uncorrectable Error Severity Register The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is cleared, the corresponding error condition is identified as nonfatal. See Table 5−10 for a complete description of the register contents.
PAGE 103
Not Recommended for New Designs PCI Express Extended Configuration Space 5.13 Secondary Error Capabilities and Control Register The secondary error capabilities and control register allows the system to monitor and control the secondary advanced error reporting capabilities. See Table 5−11 for a complete description of the register contents.
PAGE 104
Not Recommended for New Designs PCI Express Extended Configuration Space 5.14 Secondary Header Log Register The secondary header log register stores the transaction address and command for the PCI bus cycle that led to the most recently detected error condition. Offset 13Ch accesses register bits 31:0. Offset 140h accesses register bits 63:32. Offset 144h accesses register bits 95:64. Offset 148h accesses register bits 127:96. See Table 5−12 for a complete description of the register contents.
PAGE 105
Not Recommended for New Designs PCI Express Extended Configuration Space 5.16 Next Capability Offset/Capability Version Register This read-only register returns the value 000h to indicate that this extended capability block represents the end of the linked list of extended capability structures. The four least significant bits identify the revision of the current capability block as 1h.
PAGE 106
Not Recommended for New Designs PCI Express Extended Configuration Space 5.18 Port VC Capability Register 2 The second port VC capability register provides information to software regarding the VC arbitration schemes supported by the bridge. See Table 5−14 for a complete description of the register contents.
PAGE 107
Not Recommended for New Designs PCI Express Extended Configuration Space 5.19 Port VC Control Register The port VC control register allows software to configure the VC arbitration options within the bridge. See Table 5−15 for a complete description of the register contents.
PAGE 108
Not Recommended for New Designs PCI Express Extended Configuration Space 5.21 VC Resource Capability Register (VC0) The VC resource capability register for VC0 provides information to software regarding the port and arbitration schemes supported by the bridge. See Table 5−17 for a complete description of the register contents.
PAGE 109
Not Recommended for New Designs PCI Express Extended Configuration Space 5.22 VC Resource Control Register (VC0) The VC resource control register for VC0 allows software to control VC0 and the associated port and arbitration schemes supported by the bridge. See Table 5−18 for a complete description of the register contents.
PAGE 110
Not Recommended for New Designs PCI Express Extended Configuration Space 5.23 VC Resource Status Register (VC0) The VC resource status register allows software to monitor the status of the port arbitration table for this VC. See Table 5−19 for a complete description of the register contents.
PAGE 111
Not Recommended for New Designs PCI Express Extended Configuration Space 5.24 VC Resource Capability Register (VC1) The VC resource capability register for VC1 provides information to software regarding the port and arbitration schemes supported by the bridge. See Table 5−20 for a complete description of the register contents.
PAGE 112
Not Recommended for New Designs PCI Express Extended Configuration Space 5.25 VC Resource Control Register (VC1) The VC resource control register for VC1 allows software to control the second VC and associated port and arbitration schemes supported by the bridge. See Table 5−21 for a complete description of the register contents.
PAGE 113
Not Recommended for New Designs PCI Express Extended Configuration Space 5.26 VC Resource Status Register (VC1) The VC resource status register allows software to monitor the status of the port arbitration table for this VC. See Table 5−22 for a complete description of the register contents.
PAGE 114
Not Recommended for New Designs PCI Express Extended Configuration Space 5.28 Port Arbitration Table (VC1) The port arbitration table is provided to allow software to define round-robin weighting for traffic entering the PCI interface. The table is divided into 128 phases. See Table 5−26 for a complete description of the register contents. PCI Express extended register offset: Register type: Default value: 1C0h – 1FCh Read/Write 0000 0000h Table 5−25.
PAGE 115
Not Recommended for New Designs Memory-Mapped TI Proprietary Register Space 6 Memory-Mapped TI Proprietary Register Space The programming model of the memory-mapped TI proprietary register space is unique to this device. These custom registers are specifically designed to provide enhanced features associated with upstream isochronous applications. All bits marked with a k are sticky bits and are reset by a global reset (GRST) or the internally-generated power-on reset.
PAGE 116
Not Recommended for New Designs Memory-Mapped TI Proprietary Register Space 6.3 Upstream Isochrony Capabilities Register The upstream isochronous capabilities register provides software information regarding the capabilities supported by this bridge. See Table 6−2 for a complete description of the register contents.
PAGE 117
Not Recommended for New Designs Memory-Mapped TI Proprietary Register Space 6.5 Upstream Isochronous Window 0 Control Register The upstream isochronous window 0 control register allows software to identify the traffic class (TC) associated with upstream transactions targeting memory addresses in the range defined by the window. See Table 6−4 for a complete description of the register contents.
PAGE 118
Not Recommended for New Designs Memory-Mapped TI Proprietary Register Space 6.8 Upstream Isochronous Window 1 Control Register The upstream isochronous window 1 control register allows software to identify the TC associated with upstream transactions targeting memory addresses in the range defined by the window. See Table 6−5 for a complete description of the register contents.
PAGE 119
Not Recommended for New Designs Memory-Mapped TI Proprietary Register Space 6.11 Upstream Isochronous Window 2 Control Register The upstream isochronous window 2 control register allows software to identify the TC associated with upstream transactions targeting memory addresses in the range defined by the window. See Table 6−6 for a complete description of the register contents.
PAGE 120
Not Recommended for New Designs Memory-Mapped TI Proprietary Register Space 6.14 Upstream Isochronous Window 3 Control Register The upstream isochronous window 3 control register allows software to identify the TC associated with upstream transactions targeting memory addresses in the range defined by the window. See Table 6−7 for a complete description of the register contents.
PAGE 121
Not Recommended for New Designs Memory-Mapped TI Proprietary Register Space 6.17 GPIO Control Register This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior of GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO4 (SCL) and GPIO5 (SDA). This register is an alias of the GPIO control register in the classic PCI configuration space(offset B4h, see Section 4.59).
PAGE 122
Not Recommended for New Designs Memory-Mapped TI Proprietary Register Space 6.18 GPIO Data Register This register reads the state of the input mode GPIO terminals and changes the state of the output mode GPIO terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary functions share GPIO4 (SCL) and GPIO5 (SDA). The default value at power up depends on the state of the GPIO terminals as they default to general-purpose inputs.
PAGE 123
Not Recommended for New Designs Memory-Mapped TI Proprietary Register Space 6.20 Serial-Bus Word Address Register The value written to the serial-bus word address register represents the word address of the byte being read from or written to on the serial-bus interface. The word address is loaded into this register prior to writing the serial-bus slave address register that initiates the bus cycle.
PAGE 124
Not Recommended for New Designs Memory-Mapped TI Proprietary Register Space 6.22 Serial-Bus Control and Status Register The serial-bus control and status register controls the behavior of the serial-bus interface. This register also provides status information about the state of the serial-bus. This register is an alias for the serial-bus control and status register in the PCI header (offset B3h, see Section 4.58). See Table 6−11 for a complete description of the register contents.
PAGE 125
Not Recommended for New Designs Memory-Mapped TI Proprietary Register Space 6.23 TI Proprietary Register This read/write TI proprietary register is located at offset 48h and controls TI proprietary functions. This register must not be changed from the specified default state. This register is reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
PAGE 126
Not Recommended for New Designs 1394 OHCI—PCI Configuration Space 7 1394 OHCI—PCI Configuration Space The 1394 OHCI core is integrated as a PCI device behind the PCI-Express to PCI Bridge. The configuration header for the 1394 OHCI portion of the design is compliant with the PCI Specification as a standard header. Table 7−1 illustrates the configuration header that includes both the predefined portion of the configuration space and the user definable registers.
PAGE 127
Not Recommended for New Designs 1394 OHCI—PCI Configuration Space 7.2 Device ID Register The device ID register contains a value assigned to the 1394 OHCI function by Texas Instruments. The device identification for the 1394 OHCI function is 8235h. PCI register offset: Register type: Default value: 7.
PAGE 128
Not Recommended for New Designs 1394 OHCI—PCI Configuration Space 7.4 Status Register The status register provides status over the OHCI controller interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7−3 for a complete description of the register contents.
PAGE 129
Not Recommended for New Designs 1394 OHCI—PCI Configuration Space 7.5 Class Code and Revision ID Register The class code and revision ID register categorizes the OHCI controller as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See Table 7−4 for a complete description of the register contents.
PAGE 130
Not Recommended for New Designs 1394 OHCI—PCI Configuration Space 7.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the OHCI controller PCI header type and no built-in self-test. See Table 7−6 for a complete description of the register contents. PCI register offset: Register type: Default value: 0Eh Read-only 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7−6.
PAGE 131
Not Recommended for New Designs 1394 OHCI—PCI Configuration Space 7.9 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. When BIOS writes all 1s to this register, the value read back is FFFF C000h, indicating that at least 16K bytes of memory address space are required for the TI registers. See Table 7−8 for a complete description of the register contents.
PAGE 132
Not Recommended for New Designs 1394 OHCI—PCI Configuration Space 7.12 Subsystem Identification Register The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 7.24, Subsystem Access Register). See Table 7−9 for a complete description of the register contents.
PAGE 133
Not Recommended for New Designs 1394 OHCI—PCI Configuration Space 7.15 MIN_GNT and MAX_LAT Register The MIN_GNT and MAX_LAT register communicates to the system the desired setting of bits 15−8 in the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 7.6, Latency Timer and Class Cache Line Size Register). If a serial EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface.
PAGE 134
Not Recommended for New Designs 1394 OHCI—PCI Configuration Space 7.17 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 7−13 for a complete description of the register contents.
PAGE 135
Not Recommended for New Designs 1394 OHCI—PCI Configuration Space 7.19 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power management function. This register is not affected by the internally-generated reset caused by the transition from the D3hot to D0 state. See Table 7−15 for a complete description of the register contents.
PAGE 136
Not Recommended for New Designs 1394 OHCI—PCI Configuration Space 7.21 PCI PHY Control Register The PCI PHY control register provides a method for enabling the PHY CNA output. See Table 7−17 for a complete description of the register contents.
PAGE 137
Not Recommended for New Designs 1394 OHCI—PCI Configuration Space 7.22 PCI Miscellaneous Configuration Register The PCI miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 7−18 for a complete description of the register contents.
PAGE 138
Not Recommended for New Designs 1394 OHCI—PCI Configuration Space Table 7−18. Miscellaneous Configuration Register (Continued) BIT 1† FIELD NAME TYPE DISABLE_PCIGATE RW DESCRIPTION Disable PCLK test feature. This bit controls locking or unlocking the PCI clock to the 1394a OHCI core PCI bus clock input. This is a test feature only and must be cleared to 0b (all applications).
PAGE 139
Not Recommended for New Designs 1394 OHCI—PCI Configuration Space Table 7−19. Link Enhancement Control Register Description (Continued) † BIT FIELD NAME TYPE 11 RSVD R 10† enab_mpeg_ts RW 9 RSVD R 8† enab_dv_ts RW Enable DV CIP timestamp enhancement. When bit 8 is set to 1b, the enhancement is enabled for DV CIP transmit streams (FMT = 00h). The default value for this bit is 0b. 7† enab_unfair RW Enable asynchronous priority requests. OHCI-Lynx™ compatible.
PAGE 140
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8 1394 OHCI Memory-Mapped Register Space The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 7.8). These registers are the primary interface for controlling the IEEE 1394 link function. This section provides the register interface and bit descriptions.
PAGE 141
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space Table 8−1.
PAGE 142
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space Table 8−1.
PAGE 143
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.2 GUID ROM Register The GUID ROM register accesses the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI version register at OHCI offset 00h (see Section 8.1) is set to 1b. See Table 8−3 for a complete description of the register contents.
PAGE 144
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the controller attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 8−4 for a complete description of the register contents.
PAGE 145
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.5 CSR Compare Register The CSR compare register accesses the bus management CSR registers from the host through compare-swap operations. This register contains the data to be compared with the existing value of the CSR resource. OHCI register offset: Register type: Default value: 8.
PAGE 146
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See Table 8−6 for a complete description of the register contents.
PAGE 147
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 8−7 for a complete description of the register contents.
PAGE 148
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0000 0000h on a system (hardware) reset, which is an illegal GUID value.
PAGE 149
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.13 Posted Write Address Low Register The posted write address low register communicates error information if a write request is posted and an error occurs while the posted data packet is being written. See Table 8−9 for a complete description of the register contents.
PAGE 150
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.16 Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the controller. See Table 8−11 for a complete description of the register contents.
PAGE 151
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space Table 8−11. Host Controller Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 19 LPS RSC Bit 19 controls the link power status. Software must set this bit to 1b to permit the link-PHY communication. A 0b prevents link-PHY communication. The OHCI-link is divided into two clock domains (PCLK and PHY_SCLK).
PAGE 152
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.18 Self-ID Count Register The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 8−12 for a complete description of the register contents.
PAGE 153
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register enables packet receives from the upper 32 isochronous data channels. A read from either the set or clear register returns the content of the isochronous receive channel mask high register. See Table 8−13 for a complete description of the register contents.
PAGE 154
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.20 Isochronous Receive Channel Mask Low Register The isochronous receive channel mask low set/clear register enables packet receives from the lower 32 isochronous data channels. See Table 8−14 for a complete description of the register contents.
PAGE 155
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.21 Interrupt Event Register The interrupt event set/clear register reflects the state of the various interrupt sources. The interrupt bits are set to 1b by an asserting edge of the corresponding interrupt signal or by writing a 1b in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1b to the corresponding bit in the clear register.
PAGE 156
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space Table 8−15. Interrupt Event Register Description (Continued) BIT FIELD NAME TYPE 17 busReset RSCU Indicates that the PHY layer has entered bus reset mode. DESCRIPTION 16 selfIDcomplete RSCU A self-ID packet stream has been received. It is generated at the end of the bus initialization process. Bit 16 is turned off simultaneously when bit 17 (busReset) is turned on.
PAGE 157
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.22 Interrupt Mask Register The interrupt mask set/clear register enables the various interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register. In all cases except masterIntEnable (bit 31) and vendorSpecific (bit 30), the enables for each interrupt event align with the interrupt event register bits detailed in Table 8−15.
PAGE 158
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space Table 8−16. Interrupt Mask Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 15 selfIDcomplete2 RSC When this bit and bit 15 (selfIDcomplete2) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this second-self-ID-complete interrupt mask enables interrupt generation.
PAGE 159
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set to 1.
PAGE 160
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set to 1. Upon determining that the isochRx (bit 7) interrupt in the interrupt event register at OHCI offset 80h/84h (see Section 8.
PAGE 161
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.27 Initial Bandwidth Available Register The initial bandwidth available register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 8−19 for a complete description of the register contents.
PAGE 162
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.29 Initial Channels Available Low Register The initial channels available low register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 8−21 for a complete description of the register contents.
PAGE 163
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.31 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the controller. It contains controls for the receiver and cycle timer. See Table 8−23 for a complete description of the register contents.
PAGE 164
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.32 Node Identification Register The node identification register contains the address of the node on which the OHCI-Lynx™ chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15−6) and the NodeNumber field (bits 5−0) is referred to as the node ID. See Table 8−24 for a complete description of the register contents.
PAGE 165
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.33 PHY Layer Control Register The PHY layer control register reads from or writes to a PHY register. See Table 8−25 for a complete description of the register contents.
PAGE 166
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.35 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined.
PAGE 167
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space Table 8−27. Asynchronous Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 16 asynReqResource48 RSC If bit 16 is set to 1b for local bus node number 48, then asynchronous requests received by the controller from that node are accepted.
PAGE 168
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.36 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register enables asynchronous receive requests on a per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register. See Table 8−28 for a complete description of the register contents.
PAGE 169
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.37 Physical Request Filter High Register The physical request filter high set/clear register enables physical receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register.
PAGE 170
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space Table 8−29. Physical Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 16 physReqResource48 RSC If bit 16 is set to 1b for local bus node number 48, then physical requests received by the controller from that node are handled through the physical request context.
PAGE 171
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.38 Physical Request Filter Low Register The physical request filter low set/clear register enables physical receive requests on a per-node basis, and handles the lower node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the asynchronous request filter registers, then the node ID comparison is done again with this register.
PAGE 172
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.40 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See Table 8−31 for a complete description of the register contents.
PAGE 173
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.41 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the controller accesses when software enables the context by setting bit 15 (run) in the asynchronous context control register (see Section 8.40) to 1b. See Table 8−32 for a complete description of the register contents.
PAGE 174
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.42 Isochronous Transmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …, 7). See Table 8−33 for a complete description of the register contents.
PAGE 175
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.43 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the controller accesses when software enables an isochronous transmit context by setting bit 15 (run) in the isochronous transmit context control register (see Section 8.42) to 1b.
PAGE 176
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space Table 8−34. Isochronous Receive Context Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 28 multiChanMode RSC When bit 28 is set to 1b, the corresponding isochronous receive DMA context receives packets for all isochronous channels enabled in the isochronous receive channel mask high register at OHCI offset 70h/74h (see Section 8.
PAGE 177
Not Recommended for New Designs 1394 OHCI Memory-Mapped Register Space 8.46 Isochronous Receive Context Match Register The isochronous receive context match register starts an isochronous receive context running on a specified cycle number, filters incoming isochronous packets based on tag values, and waits for packets with a specified sync value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).
PAGE 178
Not Recommended for New Designs 1394 OHCI Memory-Mapped TI Extension Register Space 9 1394 OHCI Memory-Mapped TI Extension Register Space The TI extension base address register provides a method of accessing memory-mapped TI extension registers. See Section 7.9, TI Extension Base Address Register, for register bit field details. See Table 9−1 for the TI extension register listing. Table 9−1. TI Extension Register Map 9.
PAGE 179
Not Recommended for New Designs 1394 OHCI Memory-Mapped TI Extension Register Space 9.2 Isochronous Receive Digital Video Enhancements The DV frame sync and branch enhancement provides a mechanism in buffer-fill mode to synchronize 1394 DV data that is received in the correct order to DV frame-sized data buffers described by several INPUT_MORE descriptors (see 1394 Open Host Controller Interface Specification, Release 1.1).
PAGE 180
Not Recommended for New Designs 1394 OHCI Memory-Mapped TI Extension Register Space Table 9−2. Isochronous Receive Digital Video Enhancements Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 5 DV_Branch1 RSC When bit 5 is set to 1b, the isochronous receive context 1 synchronizes reception to the DV frame start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place.
PAGE 181
Not Recommended for New Designs 1394 OHCI Memory-Mapped TI Extension Register Space Table 9−3. Link Enhancement Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the OHCI controller retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward operation. 00 = Threshold ~ 2K bytes resulting in a store-and-forward operation 01 = Threshold ~ 1.
PAGE 182
Not Recommended for New Designs 1394 OHCI Memory-Mapped TI Extension Register Space 9.5 Timestamp Offset Register The value of this register is added as an offset to the cycle timer value when using the MPEG, DV, and CIP enhancements. A timestamp offset register is implemented per isochronous transmit context. The n value following the offset indicates the context number (n = 0, 1, 2, 3, …, 7). These registers are programmed by software as appropriate.
PAGE 183
Not Recommended for New Designs 1394 PHY Configuration Space 10 1394 PHY Configuration Space There are 16 accessible internal registers in the controller. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, whereas the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which 1 of 8 pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h. 10.
PAGE 184
Not Recommended for New Designs 1394 PHY Configuration Space Table 10−2. Base Register Field Descriptions FIELD SIZE TYPE DESCRIPTION Physical ID 6 R This field contains the physical address ID of this node determined during self-ID. The physical ID is invalid after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer. R 1 R Root. This bit indicates that this node is the root node.
PAGE 185
Not Recommended for New Designs 1394 PHY Configuration Space Table 10−2. Base Register Field Descriptions (Continued) FIELD SIZE TYPE DESCRIPTION 1 RW Initiate short arbitrated bus reset. This bit, if set to 1b, instructs the PHY layer to initiate a short (1.3 μs) arbitrated bus reset at the next opportunity. This bit is cleared to 0b by a bus reset. ISBR Note: Legacy IEEE Std 1394-1995 compliant PHY layers can not be capable of performing short bus resets.
PAGE 186
Not Recommended for New Designs 1394 PHY Configuration Space 10.2 Port Status Register The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. Table 10−3 shows the configuration of the port status page registers and Table 10−4 shows the corresponding field descriptions.
PAGE 187
Not Recommended for New Designs 1394 PHY Configuration Space Table 10−4. Page 0 (Port Status) Register Field Descriptions (Continued) FIELD SIZE TYPE DESCRIPTION Int_enable 1 RW Port event interrupt enable. When the Int_enable bit is set to 1b, a port event on the selected port sets the port event interrupt (Port_event) bit and notifies the link. This bit is cleared to 0b by a system (hardware) reset and is unaffected by bus reset. Fault 1 RW Fault.
PAGE 188
Not Recommended for New Designs 1394 PHY Configuration Space 10.4 Vendor-Dependent Register The vendor-dependent page provides access to the special control features of the controller, as well as to configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page_Select field in base register 7. Table 10−7 shows the configuration of the vendor-dependent page, and Table 10−8 shows the corresponding field descriptions. Table 10−7.
PAGE 189
Not Recommended for New Designs Electrical Characteristics 11 Electrical Characteristics 11.1 Absolute Maximum Ratings Over Operating Temperature Ranges † Supply voltage range: VDD_33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V VDD_15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.65 V Input voltage range, VI: PCI Express (RX) . . . . . . . . . . . . . . . . . . . . . .
PAGE 190
Not Recommended for New Designs Electrical Characteristics 11.3 PCI Express Differential Transmitter Output Ranges PARAMETER UI Unit interval VTX-DIFFp-p Differential peak-to-peak output voltage TERMINALS MIN TXP, TXN 399.88 400 MAX UNITS COMMENTS 400.12 ps Each UI is 400 ps ±300 ppm. UI does not account for SSC dictated variations. See Note 4.
PAGE 191
Not Recommended for New Designs Electrical Characteristics PCI Express Differential Transmitter Output Ranges (continued) PARAMETER TERMINALS MIN NOM MAX UNITS ITX-SHORT TX short circuit current limit TXP, TXN 90 mA The total current the transmitter can provide when shorted to its ground. UI Minimum time a transmitter must be in electrical Idle. Utilized by the receiver to start looking for an electrical idle exit after successfully receiving an electrical idle ordered set.
PAGE 192
Not Recommended for New Designs Electrical Characteristics 11.4 PCI Express Differential Receiver Input Ranges PARAMETER UI Unit interval TERMINALS MIN NOM RXP, RXN 399.88 400 MAX UNITS 400.12 ps TRX-EYE Minimum receiver eye width Each UI is 400 ps ±300 ppm. UI does not account for SSC dictated variations. See Note 9. VRX-DIFFp-p Differential input peak-to-peak voltage COMMENTS RXP, RXN RXP, RXN 0.175 1.200 0.4 V UI VRX-DIFFp-p = 2*|VRXP − VRXN| See Note 10.
PAGE 193
Not Recommended for New Designs Electrical Characteristics 11. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total UI jitter budget collected over any 250 consecutive TX UIs.
PAGE 194
Not Recommended for New Designs Electrical Characteristics 11.6 Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O) PARAMETER TEST CONDITIONS OPERATION MIN MAX UNITS VIH High-level input voltage (Note 16) VDD_33 0.7 VDD_33 VDD_33 V VIL Low-level input voltage (Note 16) VDD_33 0 0.3 VDD_33 V VI Input voltage 0 VDD_33 V VO Output voltage (Note 17) 0 VDD_33 V tT Input transition time (trise and tfall) 0 25 ns Vhys Input hysteresis (Note 18) 0.
PAGE 195
Not Recommended for New Designs Electrical Characteristics 11.8 Thermal Information XIO2200A THERMAL METRIC† † UNITS ZGW (176 PINS) θJA Junction−to−ambient thermal resistance 39.2 θJCtop Junction−to−ambient (top) thermal resistance 8.9 θJB Junction−to−board thermal resistance 20.1 ΨJT Junction−to−top charactaerization parameter 0.3 ΨJB Junction−to−board characterization parameter 20.
PAGE 196
Not Recommended for New Designs Electrical Characteristics 11.11 Jitter/Skew Characteristics for 1394a PHY Port Receiver PARAMETER Receive input jitter Receive input skew MIN TYP MAX UNITS TPA, TPB cable inputs, S100 operation ±1.08 ns TPA, TPB cable inputs, S200 operation ±0.5 ns TPA, TPB cable inputs, S400 operation ±0.315 ns Between TPA and TPB cable inputs, S100 operation ±0.8 ns Between TPA and TPB cable inputs, S200 operation ±0.
PAGE 197
Not Recommended for New Designs Glossary 12 Glossary ACRONYM DEFINITION BIST Built-in self test ECRC EEPROM End-to-end cyclic redundancy code Electrically erasable programmable read-only memory GP GPIO General purpose General-purpose input output ID IF IO I2S Identification Interface Input output Inter IC sound LPM LSB Link power management Least significant bit MSB MSI Most significant bit Message signaled interrupts PCI Peripheral component interface PME PCI power management event QoS
PAGE 198
Not Recommended for New Designs Mechanical Data 13 Mechanical Data The XIO2200A device is available in the 175−ball lead−free (Pb atomic number 82) MicroStar BGA package (ZHH), the 176-ball MicroStar BGA package (GGW), or the 176-ball lead-free (Pb atomic number 82) MicroStar BGA package (ZGW). The following figures show the mechanical dimensions for the packages. The GGW and ZGW packages are mechanically identical.
PAGE 199
PACKAGE OPTION ADDENDUM www.ti.
PAGE 200
PAGE 201
PAGE 202
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.