Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
5.10 Secondary Uncorrectable Error Status Register
The secondary uncorrectable error status register reports the status of individual PCI bus errors as they
occur. Software may only clear these bits by writing a 1b to the desired location. See Table 5-8 for a
complete description of the register contents.
PCI Express extended register offset: 12Ch
Register type: Read-only, Read/Clear
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 5-8. Secondary Uncorrectable Error Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:14 RSVD R Reserved. Returns 000 0000 0000 0000 0000b when read.
13 INTERNAL_ERROR R Internal bridge error. This error bit is associated with a PCI-X error and returns 0b when
read.
12
(1)
SERR_DETECT RCU SERR assertion detected. This bit is asserted when the bridge detects the assertion of
SERR on the secondary bus.
11
(1)
PERR_DETECT RCU PERR assertion detected. This bit is asserted when the bridge detects the assertion of
PERR on the secondary bus.
10
(1)
DISCARD_TIMER RCU Delayed transaction discard timer expired. This bit is asserted when the discard timer
expires for a pending delayed transaction that was initiated on the secondary bus.
9
(1)
UNCOR_ADDR RCU Uncorrectable address error. This bit is asserted when the bridge detects a parity error
during the address phase of an upstream transaction.
8 UNCOR_ATTRIB R Uncorrectable attribute error. This error bit is associated with a PCI-X error and returns 0b
when read.
7
(1)
UNCOR_DATA RCU Uncorrectable data error. This bit is asserted when the bridge detects a parity error during
a data phase of an upstream write transaction, or when the bridge detects the assertion of
PERR when forwarding read completion data to a PCI device.
6 UNCOR_SPLTMSG R Uncorrectable split completion message data error. This error bit is associated with a PCI-
X error and returns 0b when read.
5 UNXPC_SPLTCMP R Unexpected split completion error. This error bit is associated with a PCI-X error and
returns 0b when read.
4 RSVD R Reserved. Returns 0b when read.
3
(1)
MASTER_ABORT RCU Received master abort. This bit is asserted when the bridge receives a master abort on
the PCI interface.
2
(1)
TARGET_ABORT RCU Received target abort. This bit is asserted when the bridge receives a target abort on the
PCI interface.
1 MABRT_SPLIT R Master abort on split completion. This error bit is associated with a PCI-X error and returns
0b when read.
0 TABRT_SPLIT R Target abort on split completion status. This error bit is associated with a PCI-X error and
returns 0b when read.
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
98 PCI Express Extended Configuration Space Copyright © 2009–2012, Texas Instruments Incorporated
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