Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
5.7 Correctable Error Mask Register
The correctable error mask register controls the reporting of individual errors as they occur. When a mask
bit is set to 1b, the corresponding error status bit is not set, PCI Express error messages are blocked, the
header log is not loaded, and the first error pointer is not updated. See Table 5-6 for a complete
description of the register contents.
PCI Express extended register offset: 114h
Register type: Read-only, Read/Write
Default value: 0000 2000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 5-6. Correctable Error Mask Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:14 RSVD R Reserved. Returns 000 0000 0000 0000 0000b when read.
13
(1)
ANFEM RW Advisory Non-Fatal Error Mask.
0 = Error condition is unmasked
1 = Error condition is masked (default)
12
(1)
REPLAY_TMOUT_MAS RW Replay timer time-out mask.
K
0 = Error condition is unmasked (default)
1 = Error condition is masked
11:9 RSVD R Reserved. Returns 000b when read.
8
(1)
REPLAY_ROLL_MASK RW REPLAY_NUM rollover mask.
0 = Error condition is unmasked (default)
1 = Error condition is masked
7
(1)
BAD_DLLP_MASK RW Bad DLLP error mask.
0 = Error condition is unmasked (default)
1 = Error condition is masked
6
(1)
BAD_TLP_MASK RW Bad TLP error mask.
0 = Error condition is unmasked (default)
1 = Error condition is masked
5:1 RSVD R Reserved. Returns 00000b when read.
0
(1)
RX_ERROR_MASK RW Receiver error mask.
0 = Error condition is unmasked (default)
1 = Error condition is masked
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
96 PCI Express Extended Configuration Space Copyright © 2009–2012, Texas Instruments Incorporated
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