Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
Table 5-3. Uncorrectable Error Mask Register Description (continued)
BIT FIELD NAME ACCESS DESCRIPTION
3:0 RSVD R Reserved. Returns 0h when read.
5.5 Uncorrectable Error Severity Register
The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or
ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is
cleared, the corresponding error condition is identified as nonfatal. See Table 5-4 for a complete
description of the register contents.
PCI Express extended register offset: 10Ch
Register type: Read-only, Read/Write
Default value: 0006 2031h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1
Table 5-4. Uncorrectable Error Severity Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:22 RSVD R Reserved. Returns 000 0000 0000b when read.
21 ACS_VIOLATION_SEV R ACS violation severity. Not supported, returns 0b when read.
R
20
(1)
UR_ERROR_SEVRO RW Unsupported request error severity
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL
19
(1)
ECRC_ERROR_SEVRR RW Extended CRC error severity
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL
18
(1)
MAL_TLP_SEVR RW Malformed TLP severity
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL
17
(1)
RX_OVERFLOW_SEVR RW Receiver overflow severity
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL
16
(1)
UNXP_CPL_SEVRP RW Unexpected completion severity
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL
15
(1)
CPL_ABORT_SEVR RW Completer abort severity
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL
14
(1)
CPL_TIMEOUT_SEVR RW Completion time-out severity
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL
13
(1)
FC_ERROR_SEVR RW Flow control error severity
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL
12
(1)
PSN_TLP_SEVR RW Poisoned TLP severity
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
94 PCI Express Extended Configuration Space Copyright © 2009–2012, Texas Instruments Incorporated
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