Datasheet
XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012
www.ti.com
5.2 Next Capability Offset/Capability Version Register
This read-only register identifies the next location in the PCI Express extended capabilities link list. The
upper 12 bits in this register shall be 000h, indicating that the Advanced Error Reporting Capability is the
last capability in the linked list. The least significant four bits identify the revision of the current capability
block as 1h.
PCI Express extended register offset: 102h
Register type: Read-only
Default value: 0001h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
5.3 Uncorrectable Error Status Register
The uncorrectable error status register reports the status of individual errors as they occur on the primary
PCI Express interface. Software may only clear these bits by writing a 1b to the desired location. See
Table 5-2 for a complete description of the register contents.
PCI Express extended register offset: 104h
Register type: Read-only, Read/Clear
Default value: 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 5-2. Uncorrectable Error Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:22 RSVD R Reserved. Returns 000 0000 0000b when read.
21 ACS_VIOLATION R ACS Violation. Not supported, ths bit returns 0b when read.
20
(1)
UR_ERROR RCU Unsupported request error. This bit is asserted when an unsupported request is received.
19
(1)
ECRC_ERROR RCU Extended CRC error. This bit is asserted when an extended CRC error is detected.
18
(1)
MAL_TLP RCU Malformed TLP. This bit is asserted when a malformed TLP is detected.
17
(1)
RX_OVERFLOW RCU Receiver overflow. This bit is asserted when the flow control logic detects that the
transmitting device has illegally exceeded the number of credits that were issued.
16
(1)
UNXP_CPL RCU Unexpected completion. This bit is asserted when a completion packet is received that
does not correspond to an issued request.
15
(1)
CPL_ABORT RCU Completer abort. This bit is asserted when the bridge signals a completer abort.
14
(1)
CPL_TIMEOUT RCU Completion time-out. This bit is asserted when no completion has been received for an
issued request before the time-out period.
13
(1)
FC_ERROR RCU Flow control error. This bit is asserted when a flow control protocol error is detected either
during initialization or during normal operation.
12
(1)
PSN_TLP RCU Poisoned TLP. This bit is asserted when a poisoned TLP is received.
11:6 RSVD R Reserved. Returns 00 0000b when read.
5 SD_ERROR R Surprise down error. Not supported, this bit returns 0b when read.
4
(1)
DLL_ERROR RCU Data link protocol error. This bit is asserted if a data link layer protocol error is detected.
3:0 RSVD R Reserved. Returns 0h when read.
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
92 PCI Express Extended Configuration Space Copyright © 2009–2012, Texas Instruments Incorporated
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