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81828384858687888990
XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012
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BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Table 4-50. Cache Timer Transfer Limit Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:8 RSVD R Reserved. Returns 00h when read.
CACHE_TMR_XFR Number of PCI cycle starts that have to occur without a read hit on the completion data
7:0
(1)
RW
_LIMIT buffer, before the cache data can be discarded.
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
4.77 Cache Timer Lower Limit Register
Minimum number of clock cycles that must have passed without a read hit on the completion data buffer
before the "cache miss limit" check can be triggered. See Table 4-51 for a complete description of the
register contents.
PCI register offset: ECh
Register type: Read/Clear
Default value: 007Fh
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Table 4-51. Cache Timer Lower Limit Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:12 RSVD R Reserved. Returns 0h when read.
CACHE_TIMER Minimum number of clock cycles that must have passed without a read hit on the
11:0
(1)
RW
_LOWER_LIMIT completion data buffer before the "cache miss limit" check can be triggered.
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
4.78 Cache Timer Upper Limit Register
Discard cached data after this number of clock cycles have passed without a read hit on the completion
data buffer. See Table 4-52 for a complete description of the register contents.
PCI register offset: EEh
Register type: Read/Clear
Default value: 01C0h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0
Table 4-52. Cache Timer Upper Limit Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:12 RSVD R Reserved. Returns 0h when read.
CACHE_TIMER Discard cached data after this number of clock cycles have passed without a read hit on
11:0
(1)
RW
_UPPER_LIMIT the completion data buffer.
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
90 Classic PCI Configuration Space Copyright © 2009–2012, Texas Instruments Incorporated
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