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XIO2001

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SCPS212G –MAY 2009–REVISED DECEMBER 2012

Table 4-49. Pre-Fetch Agent Request Limits Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:12 RSVD R Reserved. Returns 0h when read.

Request count limit. Determines the number of Pre-Fetch reads that takes place in each

burst.

PFA_REQ_

11:8

(1)

RW 4'h0 = Auto-prefetch agent is disabled.

CNT_LIMIT

4'h1 = Thread is limited to one buffer. No auto-prefetch reads will be generated.

4'h2:F = Thread will be limited to initial read and (PFA_REQ_CNT_LIMIT – 1)

Completion cache mode. Determines the rules for completing the caching process.

00 = No caching.

• Pre-fetching is disabled.

• All remaining read completion data will be discarded after any of the data has been

returned to the PCI master.

01 = Light caching.

• Pre-fetching is enabled.

• All remaining read completion data will be discarded after data has been returned to

PFA_CPL_CACHE_

the PCI master and the PCI master terminated the transfer.

7:6 RW

MODE

• All remaining read completion data will be cached after data has been returned to the

PCI master and the bridge has terminated the transfer with RETRY.

10 = Full caching.

• Pre-fetching is enabled.

• All remaining read completion data will be cached after data has been returned to the

PCI master and the PCI master terminated the transfer.

• All remaining read completion data will be cached after data has been returned to the

PCI master and the bridge has terminated the transfer with RETRY.

11 = Reserved.

5:4 RSVD R Reserved. Returns 00b when read.

Request Length Limit. Determines the number of bytes in the thread that the pre-fetch

agent will read for that thread.

0000 = 64 bytes

0001 = 128 bytes

0010 = 256 bytes

PFA_REQ_LENGT

3:0 RW 0011 = 512 bytes

H_LIMIT

0100 = 1 Kbytes

0101 = 2 Kbytes

0110 = 4 Kbytes

0111 = 8 Kbytes

1000:1111 = Reserved

(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

4.76 Cache Timer Transfer Limit Register

This register is used to set the number of PCI cycle starts that have to occur without a read hit on the

completion data buffer, before the cache data can be discarded. See Table 4-50 for a complete