Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
4.74 Serial IRQ Status Register
This register indicates when a level mode IRQ is signaled on the serial IRQ stream. After a level mode
IRQ is signaled, a write-back of 1b to the asserted IRQ status bit re-arms the interrupt. IRQ interrupts that
are defined as edge mode in the serial IRQ edge control register are not reported in this status register.
See Table 4-48 for a complete description of the register contents.
PCI register offset: E4h
Register type: Read/Clear
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-48. Serial IRQ Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
IRQ 15 asserted. This bit indicates that the IRQ15 has been asserted.
15
(1)
IRQ15 RCU
0 = Deasserted
1 = Asserted
IRQ 14 asserted. This bit indicates that the IRQ14 has been asserted.
14
(1)
IRQ14 RCU
0 = Deasserted
1 = Asserted
IRQ 13 asserted. This bit indicates that the IRQ13 has been asserted.
13
(1)
IRQ13 RCU
0 = Deasserted
1 = Asserted
IRQ 12 asserted. This bit indicates that the IRQ12 has been asserted.
12
(1)
IRQ12 RCU
0 = Deasserted
1 = Asserted
IRQ 11 asserted. This bit indicates that the IRQ11 has been asserted.
11
(1)
IRQ11 RCU
0 = Deasserted
1 = Asserted
IRQ 10 asserted. This bit indicates that the IRQ10 has been asserted.
10
(1)
IRQ10 RCU
0 = Deasserted
1 = Asserted
IRQ 9 asserted. This bit indicates that the IRQ9 has been asserted.
9
(1)
IRQ9 RCU
0 = Deasserted
1 = Asserted
IRQ 8 asserted. This bit indicates that the IRQ8 has been asserted.
8
(1)
IRQ8 RCU
0 = Deasserted
1 = Asserted
IRQ 7 asserted. This bit indicates that the IRQ7 has been asserted.
7
(1)
IRQ7 RCU
0 = Deasserted
1 = Asserted
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Copyright © 2009–2012, Texas Instruments Incorporated Classic PCI Configuration Space 87
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