Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
Table 4-47. Serial IRQ Edge Control Register Description (continued)
BIT FIELD NAME ACCESS DESCRIPTION
IRQ 11 edge mode
11
(1)
IRQ11_MODE RW
0 = Edge mode (default)
1 = Level mode
IRQ 10 edge mode
10
(1)
IRQ10_MODE RW
0 = Edge mode (default)
1 = Level mode
IRQ 9 edge mode
9
(1)
IRQ9_MODE RW
0 = Edge mode (default)
1 = Level mode
IRQ 8 edge mode
8
(1)
IRQ8_MODE RW
0 = Edge mode (default)
1 = Level mode
IRQ 7 edge mode
7
(2)
IRQ7_MODE RW
0 = Edge mode (default)
1 = Level mode
IRQ 6 edge mode
6
(2)
IRQ6_MODE RW
0 = Edge mode (default)
1 = Level mode
IRQ 5 edge mode
5
(2)
IRQ5_MODE RW
0 = Edge mode (default)
1 = Level mode
IRQ 4 edge mode
4
(2)
IRQ4_MODE RW
0 = Edge mode (default)
1 = Level mode
IRQ 3 edge mode
3
(2)
IRQ3_MODE RW
0 = Edge mode (default)
1 = Level mode
IRQ 2 edge mode
2
(2)
IRQ2_MODE RW
0 = Edge mode (default)
1 = Level mode
IRQ 1 edge mode
1
(2)
IRQ1_MODE RW
0 = Edge mode (default)
1 = Level mode
IRQ 0 edge mode
0
(2)
IRQ0_MODE RW
0 = Edge mode (default)
1 = Level mode
(2) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
86 Classic PCI Configuration Space Copyright © 2009–2012, Texas Instruments Incorporated
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