Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
4.71 Arbiter Time-Out Status Register
The arbiter time-out status register contains the status of each request (request 5–0) time-out. The time-
out status bit for the respective request is set if the device did not assert FRAME after the arbiter time-out
value. See Table 4-45 for a complete description of the register contents.
PCI register offset: DEh
Register type: Read/Clear
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 4-45. Arbiter Time-Out Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
7:6 RSVD R Reserved. Returns 00b when read.
5 REQ5_TO RCU Request 5 Time Out Status
0 = No time-out
1 = Time-out has occurred
4 REQ4_TO RCU Request 4 Time Out Status
0 = No time-out
1 = Time-out has occurred
3 REQ3_TO RCU Request 3 Time Out Status
0 = No time-out
1 = Time-out has occurred
2 REQ2_TO RCU Request 2 Time Out Status
0 = No time-out
1 = Time-out has occurred
1 REQ1_TO RCU Request 1Time Out Status
0 = No time-out
1 = Time-out has occurred
0 REQ0_TO RCU Request 0 Time Out Status
0 = No time-out
1 = Time-out has occurred
4.72 Serial IRQ Mode Control Register
This register controls the behavior of the serial IRQ controller. See Table 4-46 for a complete description
of the register contents.
PCI register offset: E0h
Register type: Read-only, Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
84 Classic PCI Configuration Space Copyright © 2009–2012, Texas Instruments Incorporated
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