Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
4.70 Arbiter Request Mask Register
The arbiter request mask register enables and disables support for requests from specific masters on the
secondary bus. The arbiter request mask register also controls if a request input is automatically masked
on an arbiter time-out. See Table 4-44 for a complete description of the register contents.
PCI register offset: DDh
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 4-44. Arbiter Request Mask Register Description
BIT FIELD NAME ACCESS DESCRIPTION
7
(1)
ARB_TIMEOUT RW Arbiter time-out. This bit enables the arbiter time-out feature. The arbiter time-out is
defined as the number of PCI clocks after the PCI bus has gone idle for a device to assert
FRAME before the arbiter assumes the device will not respond.
0 = Arbiter time disabled (default)
1 = Arbiter time-out set to 16 PCI clocks
6
(1)
AUTO_MASK RW Automatic request mask. This bit enables automatic request masking when an arbiter
time-out occurs.
0 = Automatic request masking disabled (default)
1 = Automatic request masking enabled
5
(1)
REQ5_MASK RW
Request 5 (REQ5) Mask. Setting this bit forces the internal arbiter to ignore requests
signal on request input 0.
0 = Use request 5 (default)
1 = Ignore request 5
4
(1)
REQ4_MASK RW
Request 4 (REQ4) Mask. Setting this bit forces the internal arbiter to ignore requests
signal on request input 0.
0 = Use request 4 (default)
1 = Ignore request 4
3
(1)
REQ3_MASK RW
Request 3 (REQ3) Mask. Setting this bit forces the internal arbiter to ignore requests
signal on request input 0.
0 = Use request 3 (default)
1 = Ignore request 3
2
(1)
REQ2_MASK RW
Request 2 (REQ2) Mask. Setting this bit forces the internal arbiter to ignore requests
signal on request input 0.
0 = Use request 2 (default)
1 = Ignore request 2
1
(1)
REQ1_MASK RW
Request 1 (REQ1) Mask. Setting this bit forces the internal arbiter to ignore requests
signal on request input 0.
0 = Use request 2 (default)
1 = Ignore request 2
0
(1)
REQ0_MASK RW Request 0 (REQ0) Mask. Setting this bit forces the internal arbiter to ignore requests
signal on request input 0.
0 = Use request 0 (default)
1 = Ignore request 0
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Copyright © 2009–2012, Texas Instruments Incorporated Classic PCI Configuration Space 83
Submit Documentation Feedback
Product Folder Links: XIO2001