Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
4.69 Arbiter Control Register
The arbiter control register controls the bridge internal arbiter. The arbitration scheme used is a two-tier
rotational arbitration. The bridge is the only secondary bus master that defaults to the higher priority
arbitration tier. See Table 4-43 for a complete description of the register contents.
PCI register offset: DCh
Register type: Read/Write
Default value: 40h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 1 0 0 0 0 0 0
Table 4-43. Clock Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
7
(1)
Bus parking mode. This bit determines where the internal arbiter parks the secondary bus.
When this bit is set, the arbiter parks the secondary bus on the bridge. When this bit is
cleared, the arbiter parks the bus on the last device mastering the secondary bus.
PARK RW
0 = Park the secondary bus on the last secondary bus master (default)
1 = Park the secondary bus on the bridge
6
(1)
Bridge tier select. This bit determines in which tier the bridge is placed in the arbitration
scheme.
BRIDGE_TIER_SEL RW
0 = Lowest priority tier
1 = Highest priority tier (default)
5
(1)
GNT5 tier select. This bit determines in which tier GNT5 is placed in the arbitration
scheme.
TIER_SEL5 RW
0 = Lowest priority tier (default)
1 = Highest priority tier
4
(1)
GNT4 tier select. This bit determines in which tier GNT4 is placed in the arbitration
scheme.
TIER_SEL4 RW
0 = Lowest priority tier (default)
1 = Highest priority tier
3
(1)
GNT3 tier select. This bit determines in which tier GNT3 is placed in the arbitration
scheme.
TIER_SEL3 RW
0 = Lowest priority tier (default)
1 = Highest priority tier
2
(1)
GNT2 tier select. This bit determines in which tier GNT2 is placed in the arbitration
scheme.
TIER_SEL2 RW
0 = Lowest priority tier (default)
1 = Highest priority tier
1
(1)
GNT1 tier select. This bit determines in which tier GNT1 is placed in the arbitration
scheme.
TIER_SEL1 RW
0 = Lowest priority tier (default)
1 = Highest priority tier
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Copyright © 2009–2012, Texas Instruments Incorporated Classic PCI Configuration Space 81
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